UPD78F0552MA-FAA-AX Renesas Electronics America, UPD78F0552MA-FAA-AX Datasheet - Page 424
UPD78F0552MA-FAA-AX
Manufacturer Part Number
UPD78F0552MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet
1.UPD78F0551MA-FAA-AX.pdf
(822 pages)
Specifications of UPD78F0552MA-FAA-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
9
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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78K0/Kx2-L
(2) 10-bit A/D conversion result register (ADCR)
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
Note For details of wait period, refer to CHAPTER 31 CAUTIONS FOR WAIT.
Cautions 1. When writing to the A/D converter mode register 0 (ADM0), analog input channel specification
Symbol
This register is a 16-bit register that stores the A/D conversion result. The higher 6 bits are fixed to 0. Each time A/D
conversion ends, the conversion result is loaded from the successive approximation register. The higher 2 bits of the
conversion result are stored in FF09H and the lower 8 bits of the conversion result are stored in FF08H.
ADCR can be read by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
ADCR
Sampling
INTAD
ADCS
timing
Address: FF08H, FF09H
2. If data is read from ADCR, a wait cycle is generated. Do not read data from ADCR when the
0
register (ADS), and A/D port configuration registers 0, 1 (ADPC0, ADPC1), the contents of ADCR
may become undefined. Read the conversion result following conversion completion before
writing to ADM0, ADS, ADPC0, and ADPC1. Using timing other than the above may cause an
incorrect conversion result to be read.
peripheral hardware clock (f
WAIT.
ADCS
0
Figure 12-5. Format of 10-Bit A/D Conversion Result Register (ADCR)
Figure 12-4. A/D Converter Sampling and A/D Conversion Timing
period
1 or ADS rewrite
Wait
0
Note
0
FF09H
clear
SAR
After reset: 0000H
0
Sampling
PRS
0
) is stopped. For details, refer to CHAPTER 31 CAUTIONS FOR
Conversion time
R
Successive conversion
generation
to ADCR,
Transfer
INTAD
CHAPTER 12 A/D CONVERTER
clear
SAR
FF08H
Conversion time
Sampling
410
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