UPD78F0552MA-FAA-AX Renesas Electronics America, UPD78F0552MA-FAA-AX Datasheet - Page 541
UPD78F0552MA-FAA-AX
Manufacturer Part Number
UPD78F0552MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet
1.UPD78F0551MA-FAA-AX.pdf
(822 pages)
Specifications of UPD78F0552MA-FAA-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
9
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- Current page: 541 of 822
- Download datasheet (6Mb)
78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
(1) Master operation in single-master system
Note Release (SCLA0 and SDAA0 pins = high level) the I
Remark
that is communicating. If EEPROM is outputting a low level to the SDAA0 pin, for example, set the SCLA0 pin in
the output port mode, and output a clock pulse from the output port until the SDAA0 pin is constantly at high
level.
Conform to the specifications of the product that is communicating, with respect to the transmission and
reception formats.
No
No
Figure 15-29. Master Operation in Single-Master System
ACKE0 = WTIM0 = SPIE0 = 1
Setting STCEN, IICRSV = 0
IICACTL0
IICACTL0
IICWL, IICWH
Initializing I
interrupt occurs?
interrupt occurs?
interrupt occurs?
End of transfer?
IICAF0
SVA0
STCEN = 1?
ACKD0 = 1?
ACKD0 = 1?
Writing IICA
Writing IICA
Setting port
Setting port
TRC0 = 1?
IICE0 = 1
INTIICA0
STT0 = 1
INTIICA0
INTIICA0
SPT0 = 1
Restart?
START
0XX111XXB
1XX111XXB
No
Yes
2
Yes
Yes
Yes
Yes
Yes
Yes
Yes
C bus
XXH
0XH
XXH
Note
Waits for detection of the stop condition.
Yes
No
No
No
No
No
No
Prepares for starting communication
(generates a stop condition).
Starts transmission.
Waits for data transmission.
Prepares for starting communication
(generates a start condition).
Starts communication
(specifies an address and transfer
direction).
Waits for detection of acknowledge.
Setting of the port used alternatively as the pin to be used.
First, set the port to input mode and the output latch to 0 (see 15.3 (9) Port mode register 6 (PM6)).
Sets a transfer clock.
Sets a local address.
Sets a start condition.
Set the port from input mode to output mode and enable the output of the I
(see 15.3 (9) Port mode register 6 (PM6)).
SPT0 = 1
END
2
C bus in conformance with the specifications of the product
WTIM0 = WREL0 = 1
CHAPTER 15 SERIAL INTERFACE IICA
interrupt occurs?
interrupt occurs?
End of transfer?
Reading IICA
WREL0 = 1
ACKE0 = 0
ACKE0 = 1
WTIM0 = 0
INTIICA0
INTIICA0
Yes
Yes
Yes
No
No
No
Waits for data
reception.
Waits for detection
of acknowledge.
Starts reception.
2
C bus
527
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