UPD78F0513AGB-GAF-AX Renesas Electronics America, UPD78F0513AGB-GAF-AX Datasheet - Page 575
UPD78F0513AGB-GAF-AX
Manufacturer Part Number
UPD78F0513AGB-GAF-AX
Description
MCU 8BIT 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2r
Datasheet
1.UPD78F0500MC-5A4-A.pdf
(982 pages)
Specifications of UPD78F0513AGB-GAF-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Manufacturer
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Price
Company:
Part Number:
UPD78F0513AGB-GAF-AX
Manufacturer:
SEMIKRON
Quantity:
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Company:
Part Number:
UPD78F0513AGB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0/Kx2
written to IIC shift register 0 (IIC0), and the transmitting side cancels the wait state when data is written to IIC0 register.
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
(2) When master and slave devices both have a nine-clock wait
Remark
A wait may be automatically generated depending on the setting of bit 3 (WTIM0) of IIC control register 0 (IICC0).
Normally, the receiving side cancels the wait state when bit 5 (WREL0) of IICC0 register is set to 1 or when FFH is
The master device can also cancel the wait state via either of the following methods.
• By setting bit 1 (STT0) of IICC0 register to 1
• By setting bit 0 (SPT0) of IICC0 register to 1
Transfer lines
(master transmits, slave receives, and ACKE0 = 1)
Master
Slave
ACKE0: Bit 2 of IIC control register 0 (IICC0)
WREL0: Bit 5 of IIC control register 0 (IICC0)
ACKE0
SDA0
SCL0
SCL0
SCL0
IIC0
IIC0
H
Generate according to previously set ACKE0 value
D2
6
6
Master and slave both wait
after output of ninth clock
D1
7
7
D0
8
8
Figure 18-18. Wait (2/2)
ACK
9
9
Wait from
master and
slave
Wait from slave
IIC0 data write (cancel wait)
1
CHAPTER 18 SERIAL INTERFACE IIC0
D7
1
FFH is written to IIC0 or WREL0 is set to 1
D6
2
2
D5
3
3
575
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