UPD78F0533AGB-GAH-AX Renesas Electronics America, UPD78F0533AGB-GAH-AX Datasheet - Page 10
UPD78F0533AGB-GAH-AX
Manufacturer Part Number
UPD78F0533AGB-GAH-AX
Description
MCU 8BIT 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2r
Datasheet
1.UPD78F0500MC-5A4-A.pdf
(982 pages)
Specifications of UPD78F0533AGB-GAH-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
55
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F0533AGB-GAH-AX
Manufacturer:
RENESAS
Quantity:
460
Company:
Part Number:
UPD78F0533AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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CHAPTER 3 CPU ARCHITECTURE ...................................................................................................... 96
CHAPTER 4 MEMORY BANK SELECT FUNCTION (PRODUCTS WHOSE FLASH MEMORY IS AT
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ........................................... 91
3.1 Memory Space .............................................................................................................................. 96
3.2 Processor Registers................................................................................................................... 125
3.3 Instruction Address Addressing............................................................................................... 136
3.4 Operand Address Addressing .................................................................................................. 139
4.1 Memory Bank .............................................................................................................................. 148
4.2 Difference in Representation of Memory Space ..................................................................... 149
4.3 Memory Bank Select Register (BANK) ..................................................................................... 150
4.4 Selecting Memory Bank ............................................................................................................. 151
2.2.10 P130 (port 13) ............................................................................................................................... 87
2.2.11 P140 to P145 (port 14) .................................................................................................................. 88
2.2.12 AV
2.2.13 RESET .......................................................................................................................................... 90
2.2.14 REGC............................................................................................................................................ 90
2.2.15 FLMD0 .......................................................................................................................................... 90
3.1.1 Internal program memory space ................................................................................................... 111
3.1.2 Memory bank (products whose flash memory is at least 96 KB only) ........................................... 113
3.1.3 Internal data memory space.......................................................................................................... 114
3.1.4 Special function register (SFR) area ............................................................................................. 116
3.1.5 Data memory addressing .............................................................................................................. 116
3.2.1 Control registers ............................................................................................................................ 125
3.2.2 General-purpose registers............................................................................................................. 129
3.2.3 Special function registers (SFRs) .................................................................................................. 130
3.3.1 Relative addressing....................................................................................................................... 136
3.3.2 Immediate addressing ................................................................................................................... 137
3.3.3 Table indirect addressing .............................................................................................................. 138
3.3.4 Register addressing ...................................................................................................................... 139
3.4.1 Implied addressing ........................................................................................................................ 139
3.4.2 Register addressing ...................................................................................................................... 140
3.4.3 Direct addressing .......................................................................................................................... 141
3.4.4 Short direct addressing ................................................................................................................. 142
3.4.5 Special function register (SFR) addressing ................................................................................... 143
3.4.6 Register indirect addressing.......................................................................................................... 144
3.4.7 Based addressing.......................................................................................................................... 145
3.4.8 Based indexed addressing ............................................................................................................ 146
3.4.9 Stack addressing........................................................................................................................... 147
4.4.1 Referencing values between memory banks................................................................................. 151
4.4.2 Branching instruction between memory banks.............................................................................. 153
4.4.3 Subroutine call between memory banks........................................................................................ 155
4.4.4 Instruction branch to bank area by interrupt .................................................................................. 157
LEAST 96 KB ONLY)....................................................................................................... 148
REF
, AV
SS
, V
DD
, EV
DD
, V
SS
, EV
SS
............................................................................................... 89
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