UPD78F0533AGB-GAH-AX Renesas Electronics America, UPD78F0533AGB-GAH-AX Datasheet - Page 233
UPD78F0533AGB-GAH-AX
Manufacturer Part Number
UPD78F0533AGB-GAH-AX
Description
MCU 8BIT 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2r
Datasheet
1.UPD78F0500MC-5A4-A.pdf
(982 pages)
Specifications of UPD78F0533AGB-GAH-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
55
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F0533AGB-GAH-AX
Manufacturer:
RENESAS
Quantity:
460
Company:
Part Number:
UPD78F0533AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
The fastest instruction can be executed in 2 clocks of the CPU clock in the 78K0/Kx2 microcontrollers. Therefore, the
relationship between the CPU clock (f
6-2.
Address: FFFBH
Symbol
PCC
Notes 1. Bit 5 is read-only.
Cautions 1. Be sure to clear bits 3 and 7 to “0”.
Remark
CLS
CSS
2. XTSTART is used in combination with EXCLKS and OSCSELS (bits 5 and 4 of the clock
7
0
0
1
0
1
After reset: 01H
2. The peripheral hardware clock (f
f
f
operation mode select register (OSCCTL)).
subsystem clock pin.
XP
SUB
Figure 6-6. Format of Processor Clock Control Register (PCC)
:
is set.
: Subsystem clock oscillation frequency
XTSTART
Main system clock
Subsystem clock
Main system clock oscillation frequency
PCC2
(78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2)
Other than above
6
0
0
0
0
1
0
0
0
0
1
Note2
R/W
CPU
PCC1
CLS
Note 1
<5>
0
0
1
1
0
0
0
1
1
0
) and the minimum instruction execution time is as shown in Table
PCC0
CSS
<4>
0
1
0
1
0
0
1
0
1
0
CPU clock status
PRS
f
f
f
f
f
f
Setting prohibited
XP
XP
XP
XP
XP
SUB
) is not divided when the division ratio of the PCC
/2 (default)
/2
/2
/2
/2
2
3
4
3
0
See (3)
CPU clock (f
CHAPTER 6 CLOCK GENERATOR
PCC2
2
Setting of operation mode for
CPU
) selection
PCC1
1
PCC0
0
233
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