UPD78F0533AGB-GAH-AX Renesas Electronics America, UPD78F0533AGB-GAH-AX Datasheet - Page 507
UPD78F0533AGB-GAH-AX
Manufacturer Part Number
UPD78F0533AGB-GAH-AX
Description
MCU 8BIT 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2r
Datasheet
1.UPD78F0500MC-5A4-A.pdf
(982 pages)
Specifications of UPD78F0533AGB-GAH-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
55
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Company:
Part Number:
UPD78F0533AGB-GAH-AX
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UPD78F0533AGB-GAH-AX
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78K0/Kx2
(3) Timing of output to SO1n pin (first bit)
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
When communication is started, the value of transmit buffer register 1n (SOTB1n) is output from the SO1n pin. The
output operation of the first bit at this time is described below.
The first bit is directly latched by the SOTB1n register to the output latch at the falling (or rising) edge of SCK1n, and
output from the SO1n pin via an output selector. Then, the value of the SOTB1n register is transferred to the SIO1n
register at the next rising (or falling) edge of SCK1n, and shifted one bit. At the same time, the first bit of the receive
data is stored in the SIO1n register via the SI1n pin.
The second and subsequent bits are latched by the SIO1n register to the output latch at the next falling (or rising)
edge of SCK1n, and the data is output from the SO1n pin.
Remark n = 0:
n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products
Writing to SOTB1n or
Writing to SOTB1n or
reading from SIO1n
reading from SIO1n
78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2,
78K0/KD2 products
Output latch
Output latch
SOTB1n
SOTB1n
SCK1n
SCK1n
SIO1n
SIO1n
SO1n
SO1n
Figure 16-11. Output Operation of First Bit (1/2)
(b) Type 3: CKP1n = 1, DAP1n = 0
(a) Type 1: CKP1n = 0, DAP1n = 0
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
First bit
First bit
2nd bit
2nd bit
507
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