UPD78F0533AGB-GAH-AX Renesas Electronics America, UPD78F0533AGB-GAH-AX Datasheet - Page 615
UPD78F0533AGB-GAH-AX
Manufacturer Part Number
UPD78F0533AGB-GAH-AX
Description
MCU 8BIT 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2r
Datasheet
1.UPD78F0500MC-5A4-A.pdf
(982 pages)
Specifications of UPD78F0533AGB-GAH-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
55
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F0533AGB-GAH-AX
Manufacturer:
RENESAS
Quantity:
460
Company:
Part Number:
UPD78F0533AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
(1) Start condition ~ address
Notes 1. Write data to IIC0, not setting WREL0, in order to cancel a wait state during master transmission.
WREL0
INTIIC0
WREL0
INTIIC0
ACKD0
MSTS0
ACKD0
MSTS0
WTIM0
ACKE0
WTIM0
ACKE0
Transfer lines
Processing by master device
Processing by slave device
SPD0
TRC0
SDA0
SPD0
TRC0
STD0
SPT0
SCL0
STD0
SPT0
STT0
STT0
2. To cancel slave wait, write “FFH” to IIC0 or set WREL0.
IIC0
IIC0
Start condition
H
H
H
H
L
L
L
L
L
L
(When 9-Clock Wait Is Selected for Both Master and Slave) (1/3)
Receive
IIC0
AD6 AD5 AD4 AD3 AD2 AD1 AD0
Figure 18-27. Example of Master to Slave Communication
1
Transmit
address
2
3
4
5
6
7
W
8
ACK
9
CHAPTER 18 SERIAL INTERFACE IIC0
IIC0
IIC0
D7
1
Note 2
data Note 1
D6
FFH Note 2
2
D5
3
D4
4
615
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