UPD78F1143AGA-HAB-AX Renesas Electronics America, UPD78F1143AGA-HAB-AX Datasheet - Page 200
UPD78F1143AGA-HAB-AX
Manufacturer Part Number
UPD78F1143AGA-HAB-AX
Description
MCU 16BIT 78K0R/KX3 64-TQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1143AGA-HAB-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1143AGA-HAB-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(b) Start timing in event counter mode
(c) Start timing in capture mode
Caution In the first cycle operation of count clock after writing TS0n, an error at a maximum of one
<1> While TE0n is set to 0, TCR0n holds the initial value.
<2> Writing 1 to TS0n sets 1 to TE0n.
<3> As soon as 1 has been written to TS0n and 1 has been set to TE0n, the "TDR0n value" is loaded to
<4> After that, the TCR0n value is counted down according to the count clock.
<1> Writing 1 to TS0n sets TE0n = 1
<2> The write data to TS0n is held until count clock generation.
<3> TCR0n holds the initial value until count clock generation.
<4> On generation of count clock, 0000H is loaded to TCR0n and count starts.
Start trigger detection signal
TCR0n to start counting.
clock is generated since count start delays until count clock has been generated. When the
information on count start timing is necessary, an interrupt can be generated at count start
by setting MD0n0 = 1.
Start trigger detection signal
TS0n (write) hold signal
TS0n (write) hold signal
TS0n (write)
Count clock
TS0n (write)
Count clock
Figure 6-11. Start Timing (In Event Counter Mode)
INTTM0n
TCR0n
TE0n
Figure 6-12. Start Timing (In Capture Mode)
TCR0n
TE0n
f
CLK
f
CLK
CHAPTER 6 TIMER ARRAY UNIT
<1>
<1>
Initial value
User’s Manual U17854EJ9V0UD
<1>
<2>
<2>
Initial value
<3>
<3>
TDR0n value
When MD0n0 = 1 is set
0000H
TDR0n value-1
<4>
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