UPD78F1142AF1-AN1-A Renesas Electronics America, UPD78F1142AF1-AN1-A Datasheet - Page 182
UPD78F1142AF1-AN1-A
Manufacturer Part Number
UPD78F1142AF1-AN1-A
Description
MCU 16BIT 78K0R/KX3 64-FBGA
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1142AF1-AN1-A
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1142AF1-AN1-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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5.6.8 Conditions before clock oscillation is stopped
conditions before the clock oscillation is stopped.
180
Internal high-speed
oscillation clock
X1 clock
External main system clock
Subsystem clock
Remarks 1. f
The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and
Clock
2. The number of clocks listed in Table 5-7 to Table 5-9 is the number of CPU clocks before switchover.
3. Calculate the number of clocks in Table 5-7 to Table 5-9 by removing the decimal portion.
Set Value Before Switchover
Table 5-10. Conditions Before the Clock Oscillation Is Stopped and Flag Settings
Example When switching the main system clock from the internal high-speed oscillation clock to the
f
f
f
f
f
MX
MAIN
MAINC
SUB
CLK
IH
(f
(f
:Internal high-speed oscillation clock frequency
:High-speed system clock frequency
:Main system clock frequency
:Main system select clock frequency
:Subsystem clock frequency
:CPU/peripheral hardware clock frequency
CLK
CLK
CSS
= f
= f
0
1
high-speed system clock (@ oscillation with f
Table 5-9. Maximum Number of Clocks Required in Type 3
MCS = 1 or CLS = 1
(The CPU is operating on a clock other than the internal high-speed
oscillation clock)
MCS = 0 or CLS = 1
(The CPU is operating on a clock other than the high-speed system clock)
CLS = 0
(The CPU is operating on a clock other than the subsystem clock)
SUB
MAINC
1 + f
/2)
)
IH
/f
MX
= 1 + 8/10 = 1 + 0.8 = 1.8 → 2 clocks
Conditions Before Clock Oscillation Is Stopped
CHAPTER 5 CLOCK GENERATOR
User’s Manual U17854EJ9V0UD
(External Clock Input Disabled)
2 + f
(f
SUB
CLK
/2f
= f
0
MAINC
MAINC
Set Value After Switchover
clock
)
IH
CSS
= 8 MHz, f
1 + 4 f
(f
MX
CLK
MAINC
= 10 MHz)
= f
1
/f
SUB
SUB
/2)
clock
HIOSTOP = 1
MSTOP = 1
XTSTOP = 1
Flag Settings of SFR
Register
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