UPD70F3736GK-GAK-AX Renesas Electronics America, UPD70F3736GK-GAK-AX Datasheet - Page 350
UPD70F3736GK-GAK-AX
Manufacturer Part Number
UPD70F3736GK-GAK-AX
Description
MCU 32BIT V850ES/JX3-L 80-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3736GK-GAK-AX.pdf
(830 pages)
Specifications of UPD70F3736GK-GAK-AX
Package / Case
*
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Speed
20MHz
Number Of I /o
66
Core Processor
RISC
Program Memory Type
FLASH
Ram Size
16K x 8
Program Memory Size
256KB (256K x 8)
Data Converters
A/D 8x10b, D/A 1x8b
Oscillator Type
Internal
Peripherals
DMA, LVD, PWM, WDT
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3736GK-GAK-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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detected, the count value of the 16-bit counter is stored in the TQ0CCRm register, and a capture interrupt request
signal (INTTQ0CCm) is generated.
generates an overflow interrupt request signal (INTTQ0OV) at the next clock, is cleared to 0000H, and continues
counting. At this time, the overflow flag (TQ0OVF bit) is also set to 1. Clear the overflow flag to 0 by executing the
CLR instruction by software.
350
When the TQ0CE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIQ0m pin is
The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it
INTTQ0CC0 signal
INTTQ0CC1 signal
INTTQ0CC2 signal
INTTQ0CC3 signal
TQ0CCR0 register
TQ0CCR1 register
TQ0CCR2 register
TQ0CCR3 register
INTTQ0OV signal
TIQ00 pin input
TIQ01 pin input
TIQ02 pin input
TIQ03 pin input
16-bit counter
Figure 8-30. Basic Timing in Free-Running Timer Mode (Capture Function)
TQ0OVF bit
TQ0CE bit
FFFFH
0000H
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
0000
0000
0000
0000
D
20
D
Preliminary User’s Manual U18952EJ1V0UD
00
D
30
D
10
D
Cleared to 0 by
CLR instruction
00
D
D
20
D
01
D
10
30
D
11
D
21
D
31
D
01
Cleared to 0 by
CLR instruction
D
11
D
12
D
D
D
21
02
31
D
22
D
32
D
D
CLR instruction
Cleared to 0 by
02
12
D
03
D
D
D
13
32
22
D
D
33
03
D
23
D
13
D
D
33
23
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