UPD70F3736GK-GAK-AX Renesas Electronics America, UPD70F3736GK-GAK-AX Datasheet - Page 692
UPD70F3736GK-GAK-AX
Manufacturer Part Number
UPD70F3736GK-GAK-AX
Description
MCU 32BIT V850ES/JX3-L 80-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3736GK-GAK-AX.pdf
(830 pages)
Specifications of UPD70F3736GK-GAK-AX
Package / Case
*
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Speed
20MHz
Number Of I /o
66
Core Processor
RISC
Program Memory Type
FLASH
Ram Size
16K x 8
Program Memory Size
256KB (256K x 8)
Data Converters
A/D 8x10b, D/A 1x8b
Oscillator Type
Internal
Peripherals
DMA, LVD, PWM, WDT
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3736GK-GAK-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Item
LVI
Subclock oscillator
Internal oscillator
PLL
CPU
DMA
Interrupt controller
Timer P (TMP0 to TMP2, TMP5)
Timer Q (TMQ0)
Timer M (TMM0)
Watch timer
Watchdog timer 2
Serial interface
A/D converter
D/A converter
Real-time output function (RTO)
Key interrupt function (KR)
CRC operation circuit
External bus interface
Port function
Internal data
Note Be sure to stop the PLL (PLLCTL.PLLON bit = 0) before stopping the main clock.
Caution When the CPU is operating on the subclock and main clock oscillation is stopped, accessing a
Setting of Subclock Operation Mode
register in which a wait occurs is disabled. If a wait is generated, it can be released only by reset
(see 3.4.8 (2)).
CSIB0 to CSIB2
I
UARTA0 to UARTA2
2
C00, I
2
C01
Table 21-11. Operating Status in Subclock Operation Mode
Operable
Oscillates
Oscillation enabled
Operable
Operable
Operable
Operable
Operable
Operable
Operable
Operable
Operable
Operable
Operable
Operable
Operable
Operable
Operable
Operable
Operable
See 2.2 Pin States.
Settable
Settable
CHAPTER 21 STANDBY FUNCTION
Preliminary User’s Manual U18952EJ1V0UD
When Main Clock Is Oscillating
Operating Status
Stops operation
Stops operation
Stops operation
Operable when f
the count clock
Operable when f
count clock
Operable when f
the count clock
Operable when the SCKBn input clock is
selected as the count clock (n = 0 to 2)
Stops operation
Stops operation (but UARTA0 is
operable when the ASCKA0 input clock
is selected)
Stops operation
Stops operation (output held)
When Main Clock Is Stopped
Note
R
XT
R
/8 or f
or f
is selected as the
XT
XT
is selected as
is selected as
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