UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 233

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) PWM output
Remarks 1. 0/1: Set to 0 or 1 as necessary
Figure 7-11. Contents of Register Settings When 16-Bit Timer/Event Counter Is Used for PWM Output
TMCn0
TMCn1
By setting the TMCn0 and TMCn1 registers as shown in Figure 7-11, the 16-bit timer/event counter can output
a PWM signal, whose frequency is determined according to the setting of the CSn2 to CSn0 bits of the TMCn0
register, with the values that were preset in the CCn0 and CCn1 registers determining the intervals.
When the counter value of the TMn register matches the setting value of the CCn0 register, the TOn output
becomes active. Then, when the counter value of the TMn register matches the setting value of the CCn1
register, the TOn output becomes inactive. The TMn register continues counting. When it overflows, its count
value is cleared to 0000H, and the register continues counting. In this way, a PWM signal whose frequency is
determined according to the setting of the CSn2 to CSn0 bits of the TMCn0 register can be output. When the
setting value of the CCn0 register and the setting value of the CCn1 register are the same, the TOn output
remains inactive and does not change.
The active level of the TOn output can be set by the ALVn bit of the TMCn1 register.
Remark
2. n = 0, 1
OVFn
OSTn ENTOn ALVn ETIn CCLRn
0/1
0
n = 0, 1
CSn2 CSn1 CSn0
0/1
1
0/1
0/1
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 0 AND 1
0/1
0/1
0
0
User’s Manual U15905EJ2V1UD
ECLRn
0/1
0
CMSn1 CMSn0
TMCEn TMCAEn
1
1
1
1
Supply input clocks to internal units
Enable count operation
Use CCn0 register as compare register
Use CCn1 register as compare register
Disable clearing of TMn register due to
match with CCn0 register
Enable external pulse output (TOn)
Continue counting after TMn register
overflows
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