UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 397

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.13 Communication Reservation
to enable transmission of a start condition when the bus is released. There are two modes under which the bus is not
used.
To start master device communications when not currently using a bus, a communication reservation can be made
• When arbitration results in neither master nor slave operation
• When an extension code is received and slave operation is disabled (ACK is not returned and the bus was
If bit 1 (STT) of IICC is set while the bus is not being used, a start condition is automatically generated and the wait
status is set after the bus is released (after a stop condition is detected).
When the bus release is detected (when a stop condition is detected), writing to the IIC shift register (IIC) causes
the master’s address transfer to start. At this point, bit 4 (SPIE) of IICC should be set.
When the STT bit has been set, the operation mode (as start condition or as communication reservation) is
determined according to the bus status.
If the bus has been released ...................................................a start condition is generated
If the bus has not been released (standby mode) ...................communication reservation
To detect which operation mode has been determined for the STT bit, set the STT bit, wait for the wait period, then
check the MSTS (bit 7 of IIC status register (IICS)).
Wait periods, which should be set via software, are listed in Table 15-6. These wait periods can be set via the
settings for bits 3, 1, and 0 (SMC, CL1, and CL0) in the IIC clock selection register (IICCL).
released when bit 6 (LREL) of the IIC control register (IICC) was set to “1”).
SMC
0
0
0
0
1
1
1
1
CL1
0
0
1
1
0
0
1
1
Table 15-6. Wait Periods
User’s Manual U15905EJ2V1UD
CHAPTER 15 I
CL0
0
1
0
1
0
1
0
1
2
C BUS
26 clocks
46 clocks
92 clocks
37 clocks
16 clocks
32 clocks
13 clocks
Wait Period
395