UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 465
UPD70F3201YGC-YEU-A
Manufacturer Part Number
UPD70F3201YGC-YEU-A
Description
MCU 32BIT I2C 100TQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Sx2r
Datasheet
1.UPD70F3201YGC-YEU-A.pdf
(555 pages)
Specifications of UPD70F3201YGC-YEU-A
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
68
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 2.7 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3201YGC-YEU-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Item
Main clock oscillator
Subclock oscillator
CPU
DMA
Interrupt controller
ROM correction
16-bit timer/event counters (TM0, TM1)
8-bit timer/event counters (TM2 to TM5)
Real-time counter
Watchdog timer
Serial interface
A/D converter
D/A converter
External bus interface
Port function
Internal data
(2) Releasing IDLE mode by RESET pin input
Notes 1.
The same operation as the normal reset operation is performed.
2. If the IDLE mode is set immediately after the D/A conversion has started (during conversion), the
µ
operation continues until the D/A conversion is completed, when the D/A conversion is completed, the
output is retained.
PD703200Y, 703201Y, 703204Y, 70F3201Y, and 70F3204Y only
Setting of IDLE Mode
CSI0 to CSI4
I
UART0, UART1
2
C
Note 1
Table 18-5. Operation Status in IDLE Mode
Oscillation enabled
Stops operation
Stops operation
Stops operation
Stops operation
Stops operation
Stops operation
Operable when divided f
selected as count clock
Stops operation
Operable when SCKn input clock is selected as operation clock (n = 0 to 4)
Stops operation
Stops operation
Operable when f
Stops operation (output is retained)
Refer to CHAPTER 5 BUS CONTROL FUNCTION.
Retains status before IDLE mode was set.
The CPU registers, statuses, data, and all other internal data such as the contents of
the internal RAM are retained as they were before the IDLE mode was set.
CHAPTER 18 STANDBY FUNCTION
User’s Manual U15905EJ2V1UD
When Subclock Is Not Used
BRG
−
is selected as operation clock
X
/BRG output is
Operation Status
Note 2
Oscillation enabled
Operable
When Subclock Is Used
463
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