UPD70F3739GC-UEU-AX Renesas Electronics America, UPD70F3739GC-UEU-AX Datasheet - Page 344
UPD70F3739GC-UEU-AX
Manufacturer Part Number
UPD70F3739GC-UEU-AX
Description
MCU 32BIT V850ES/JX3 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3r
Datasheet
1.UPD70F3739GC-UEU-AX.pdf
(889 pages)
Specifications of UPD70F3739GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
32MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3739GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 344 of 889
- Download datasheet (11Mb)
V850ES/JG3
8.5.4
to 1. When the valid edge of an external trigger input is detected, 16-bit timer/event counter Q starts counting, and outputs
a one-shot pulse from the TOQ01 to TOQ03 pins.
is used, the TOQ00 pin outputs the active level while the 16-bit counter is counting, and the inactive level when the counter
is stopped (waiting for a trigger).
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
In the one-shot pulse output mode, 16-bit timer/event counter Q waits for a trigger when the TQ0CTL0.TQ0CE bit is set
Instead of the external trigger, a software trigger can also be generated to output the pulse. When the software trigger
TIQ00 pin
One-shot pulse output mode (TQ0MD2 to TQ0MD0 bits = 011)
Count clock
selection
Software trigger
generation
TQ0CE bit
detector
Edge
Figure 8-20. Configuration in One-Shot Pulse Output Mode
Count start
control
CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
CCR1 buffer
TQ0CCR1
register
register
CCR0 buffer register
Match signal
TQ0CCR0 register
16-bit counter
CCR2 buffer
TQ0CCR2
register
register
Match signal
CCR3 buffer
TQ0CCR3
register
register
Match signal
Match signal
Transfer
Transfer
Transfer
Clear
Transfer
S
R
S
R
S
R
S
R
controller
controller
controller
controller
(RS-FF)
(RS-FF)
(RS-FF)
(RS-FF)
Output
Output
Output
Output
INTTQ0CC1 signal
INTTQ0CC2 signal
INTTQ0CC3 signal
INTTQ0CC0 signal
Page 328 of 870
TOQ01 pin
TOQ02 pin
TOQ03 pin
TOQ00 pin
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