UPD70F3739GC-UEU-AX Renesas Electronics America, UPD70F3739GC-UEU-AX Datasheet - Page 768
UPD70F3739GC-UEU-AX
Manufacturer Part Number
UPD70F3739GC-UEU-AX
Description
MCU 32BIT V850ES/JX3 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3r
Datasheet
1.UPD70F3739GC-UEU-AX.pdf
(889 pages)
Specifications of UPD70F3739GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
32MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Price
Company:
Part Number:
UPD70F3739GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3
28.2 Debugging Without Using DCU
and TXDA0), pins for CSIB0 (SIB0, SOB0, SCKB0, and HS (PCM0)), or pins for CSIB3 (SIB3, SOB3, SCKB3, and HS
(PCM0)) as debug interfaces, without using the DCU.
28.2.1 Circuit connection examples
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
The following describes how to implement an on-chip debug function using MINICUBE2 with pins for UARTA0 (RXDA0
Notes 1. Connect TXDA0/SOB0/SOB3 (transmit side) of the V850ES/JG3 to RXD/SI (receive side) of the
Remark Refer to Table 28-3 for pins used when UARTA0, CSIB0, or CSIB3 is used for communication interface.
Figure 28-3. Circuit Connection Example When UARTA0/CSIB0/CSIB3 Is Used for Communication Interface
2. The V850ES/JG3-side pin connected to this pin (FLMD0, FLMD1) can be used as an alternate-
3. This connection is designed assuming that the RESET signal is output from the N-ch open-drain
4. The circuit enclosed by a dashed line is designed for flash self programming, which controls the
target connector, and TXD/SO (transmit side) of the target connector to RXDA0/SIB0/SIB3 (receive
side) of the V850ES/JG3.
function pin other than while the memory is rewritten during a break in debugging, because this pin is
in a Hi-Z state.
buffer (output resistance: 100 Ω or less).
FLMD0 pin via ports.
programming is not performed, a pull-down resistance for the FLMD0 pin can be within 1 kΩ to 10
kΩ.
RESET_IN
RESET_OUT
QB-MINI2
TXD/SO
RXD/SI
FLMD1
FLMD0
GND
VDD
SCK
Note 1
Note 1
CLK
Note 2
Note 2
Note 3
HS
V
DD
Use the port for inputting or outputting the high level.
V
V
DD
DD
V
DD
CHAPTER 28 ON-CHIP DEBUG FUNCTION
RESET signal
V
DD
V
RESET
TXDA0/SOB0/SOB3
V
RXDA0/SIB0/SIB3
SCKB0/SCKB3
HS (PCM0)
FLMD1
FLMD0
Port X
DD
SS
Reset circuit
V850ES/JG3
When flash self
Note 4
Page 752 of 870
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