UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 209
UPD70F3771GF-GAT-AX
Manufacturer Part Number
UPD70F3771GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-H 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Hr
Datasheet
1.UPD70F3760GC-UEU-AX.pdf
(1512 pages)
Specifications of UPD70F3771GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CAN, CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3771GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-H, V850ES/JH3-H
6.5
6.5.1
output by the PLL function or the clock-through mode can be selected as the operating clock of the CPU and on-chip
peripheral functions.
6.5.2
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
In the V850ES/JG3-H and V850ES/JH3-H, an operating clock that is 8 times higher than the oscillation frequency
When PLL function is used (×8): Input clock = 3.0 to 6.0 MHz (output: 24 to 48 MHz)
Clock-through mode:
(1) PLL control register (PLLCTL)
Cautions 1. When the PLLON bit is cleared to 0, the SELPLL bit is automatically cleared to 0 (clock-
PLL Function
The PLLCTL register is an 8-bit register that controls the PLL function.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 01H.
Overview
Registers
2. The SELPLL bit can be set to 1 only when the PLL clock frequency is stabilized. If not
PLLCTL
through mode).
(unlocked), "0" is written to the SELPLL bit if data is written to it.
After reset: 01H
SELPLL
PLLON
0
0
1
0
1
PLL stopped
PLL operating
(After PLL operation starts, a lockup time is required for frequency stabilization)
Clock-through mode
PLL mode
Input clock = 3.0 to 6.0 MHz (output: 3.0 to 6.0 MHz)
R/W
0
Address: FFFFF82CH
0
CPU operation clock selection register
PLL operation stop register
0
CHAPTER 6 CLOCK GENERATION FUNCTION
0
0
SELPLL
< >
PLLON
< >
Page 209 of 1509
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