UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 745
UPD70F3771GF-GAT-AX
Manufacturer Part Number
UPD70F3771GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-H 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Hr
Datasheet
1.UPD70F3760GC-UEU-AX.pdf
(1512 pages)
Specifications of UPD70F3771GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CAN, CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3771GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-H, V850ES/JH3-H
17.6.5 UART transmission
writing transmit data to the UCnTX register. The start bit, parity bit, and stop bit are automatically added.
enabled at the transmit destination.
operation.
the UCnTX register to the UARTCn transmit shift register, and thereafter the contents of the UARTCn transmit shift register
are output to the TXDCn pin.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
A high level is output to the TXDCn pin by setting the UCnCTL0.UCnPWR bit to 1.
Next, the transmission enabled status is set by setting the UCnCTL0.UCnTXE bit to 1, and transmission is started by
Since the CTS (transmit enable signal) input pin is not provided in UARTCn, use a port to check that reception is
The data in the UCnTX register is transferred to the UARTCn transmit shift register upon the start of the transmit
A transmission enable interrupt request signal (INTUCnT) is generated upon completion of transmission of the data of
Write of the next transmit data to the UCnTX register is enabled after the INTUCnT signal is generated.
Remark
TXDCn
INTUCnT
LSB first
Start
bit
D0
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
Figure 17-12. UART Transmission
D1
D2
D3
D4
D5
D6
D7
Parity
bit
Stop
bit
Page 745 of 1509
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