SAF-C515C-8EM CA Infineon Technologies, SAF-C515C-8EM CA Datasheet
SAF-C515C-8EM CA
Specifications of SAF-C515C-8EM CA
F515C8EMCAXT
SAF-C515C-8EMCA
SAF-C515C-8EMCA
SAF-C515C-8EMCAIN
SAFC515C8EMCAX
SP000068749
SP000106399
Related parts for SAF-C515C-8EM CA
SAF-C515C-8EM CA Summary of contents
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C515C ...
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... Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
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C515C ...
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... Previous Version: Page Subjects (major changes since last revision) Enhanced Hooks Technology™ trademark of Infineon Technologies. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. ...
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Single-Chip Microcontroller Features • Full upward compatibility with SAB 80C515A • On-chip program memory (with optional memory protection) – C515C-8R 64 Kbytes on-chip ROM – C515C-8E 64 Kbytes on-chip OTP – alternatively Kbytes external program memory ...
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... DD • P-MQFP-80-1 package • Temperature Ranges: SAB-C515C versions: T SAF-C515C versions: SAH-C515C versions: Note: Versions for extended temperature range - 110 C (SAH-C515C) are available on request. The C515C is an enhanced, upgraded version of the SAB 80C515A 8-bit microcontroller which additionally provides a full CAN interface, a SPI compatible synchronous serial interface, extended power save provisions, additional on-chip RAM, 64K of on-chip program memory, two new external interrupts and RFI related improvements ...
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... Note: The term C515C refers to all versions described within this document unless otherwise noted. Ordering Information The ordering code for Infineon Technologies’ microcontrollers provides an exact reference to the required product. This ordering code identifies: • The derivative itself, i.e. its function set • ...
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XTAL1 XTAL2 ALE PSEN EA RESET PE/SWD HWPD CPUR V SSE1 V DDE1 V SSE2 V DDE2 V SS1 V DD1 Figure 2 Logic Symbol Data Sheet V V AGND AREF Port 0 8 Bit Digital I/O Port 1 8 ...
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P5.6 61 P5.5 62 P5.4 63 P5.3 64 P5.2 65 P5 DDE2 HWPD SSE2 N.C. 71 P4.0/ADST 72 P4.1/SCLK 73 P4.2/SRI 74 PE/SWD 75 P4.3/STO 76 P4.4/SLS 77 P4.5/INT8 ...
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Table 2 Pin Definitions and Functions Symbol Pin Number P-MQFP-80-1 RESET AREF V 4 AGND P6.0-P6.7 12-5 P7.0 / INT7 23 Data Sheet 1) I/O Function I RESET A low level on this pin for the duration ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Number P-MQFP-80-1 P3.0-P3.7 15- Data Sheet 1) I/O Function I/O Port 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Number P-MQFP-80-1 P1.0 - P1.7 31- XTAL2 36 Data Sheet 1) I/O Function I/O Port 8-bit quasi-bidirectional I/O port with ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Number P-MQFP-80-1 XTAL1 37 P2.0-P2.7 38-45 CPUR 46 PSEN 47 Data Sheet 1) I/O Function O XTAL1 Output of the inverting oscillator amplifier. I/O Port 8-bit quasi-bidirectional I/O ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Number P-MQFP-80-1 ALE P0.0-P0.7 52-59 P5.0-P5.7 67-60 Data Sheet 1) I/O Function O The Address Latch Enable output is used for latching the address into external memory during ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Number P-MQFP-80-1 HWPD 69 P4.0-P4.7 72-74, 76- Data Sheet 1) I/O Function I Hardware Power Down A low level on this pin for ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Number P-MQFP-80-1 PE/SWD SSCLK V 14 DDCLK V 32 DDE1 V 68 DDE2 V 35 SSE1 V 70 SSE2 V 33 DD1 V 34 SS1 Data Sheet 1) ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Number P-MQFP-80 DDEXT V 51 SSEXT N. Input Output Data Sheet 1) I/O Function – Supply voltage for external access pins This ...
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Oscillator Watchdog XTAL1 OSC & Timing XTAL2 ALE PSEN 8 Datapointers EA Programmable CPUR Watchdog Timer PE/SWD HWPD Timer 0 RESET Timer 1 Timer 2 Capture Compare Unit USART Baud Rate Generator SSC (SPI) Interface Full-CAN Controller Interrupt Unit V ...
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CPU The C515C is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting ...
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Memory Organization The C515C CPU manipulates data and operands in the following five address spaces: • Kbytes of internal/external program memory • Kbytes of external data memory • 256 bytes of internal data memory ...
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Control of XRAM/CAN Controller Access The XRAM in the C515C is a memory area that is logically located at the upper end of the external memory space, but is integrated on the chip. Because the XRAM and the CAN controller ...
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The XRAM/CAN controller can be accessed by read/write instructions (MOVX A,DPTR, MOVX @DPTR,A), which use the 16-bit DPTR for indirect addressing. For accessing the XRAM or CAN controller, the effective address stored in DPTR must be in the range of ...
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Table 3 Behaviour of P0/P2 and RD/WR During MOVX Accesses MOVX DPTR @DPTR < XRAM/CAN address range DPTR XRAMCAN address range MOVX XPAGE @ Ri < XRAMCAN addr. page range XPAGE XRAMCAN addr. page range EA = ...
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Reset and System Clock The reset input is an active low input at pin RESET. Since the reset is synchronized internally, the RESET pin must be held low for at least two machine cycles (12 oscillator periods) while the oscillator ...
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Crystal/Resonator Oscillator Mode MHz C Crystal Mode : ± (incl. stray capacitance) Resonator Mode : C = depends on selected ceramic resonator Figure 7 Recommended Oscillator Circuitries Multiple Datapointers As ...
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Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of ...
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Special Function Registers The registers, except the program counter and the four general purpose register banks, reside in the special function register area. The special function register area consists of two portions: the standard special function register area and the ...
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Table 4 Special Function Registers - Functional Block Block Symbol Name CPU ACC Accumulator B B-Register DPH Data Pointer, High Byte DPL Data Pointer, Low Byte DPSEL Data Pointer Select Register PSW Program Status Word Register SP Stack Pointer 1) ...
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Table 4 Special Function Registers - Functional Block (cont’d) Block Symbol Name 1) Serial ADCON0 A/D Converter Control Register 0 1) Channel PCON Power Control Register SBUF Serial Channel Buffer Register SCON Serial Channel Control Register SRELL Serial Channel Reload ...
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Table 4 Special Function Registers - Functional Block (cont’d) Block Symbol Name SSC SSCCON SSC Control Register Interface STB SSC Transmit Buffer SRB SSC Receive Register SCF SSC Flag Register SCIEN SSC Interrupt Enable Register SSCMOD SSC Mode Test Register ...
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Table 5 Contents of the SFRs, SFRs in Numeric Order of their Addresses Addr. Register Content after 1) Reset DPL DPH ...
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Table 5 Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont’d) Addr. Register Content after 1) Reset AA SRELL SCF XXXX- H XX00 B AC SCIEN XXXX- H XX00 ...
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Table 5 Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont’d) Addr. Register Content after 1) Reset 2) D0 PSW ADCON0 ADDATH ADDATL 00XX- ...
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Table 6 Contents of the CAN Registers in Numeric Order of their Addresses Addr. Regis- Content ter after H Reset F700 F701 F702 ...
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Table 6 Contents of the CAN Registers in Numeric Order of their Addresses (cont’d) Addr. Regis- Content ter after H Reset F7nC DB5n F7nD DB6n F7nE DB7n XX ...
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Digital I/O Ports The C515C allows for digital I lines grouped into 6 bidirectional 8-bit ports and one 1-bit port. Each port bit consists of a latch, an output driver and an input buffer. Read and write accesses ...
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Port Structure Selection of Port 5 After a reset operation of the C515C, the quasi-bidirectional 8051-compatible port structure is selected. For selection of the bidirectional (CMOS) port 5 structure the bit PMOD of SFR SYSCON must be set. Because each ...
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Timer / Counter 0 and 1 Timer / Counter 0 and 1 can be used in four operating modes as listed in Table 7 Timer/Counter 0 and 1 Operating Modes Mode Description 0 8-bit timer/counter with a divide-by-32 prescaler 1 ...
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Timer / Counter 2 with Compare/Capture/Reload The timer 2 of the C515C provides additional compare/capture/reload features, which allow the selection of the following operating modes: • Compare PWM signals with 16-bit/600 ns resolution • Capture ...
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Timer 2 Operating Modes The timer 2, which is a 16-bit-wide register, can operate as timer, event counter, or gated timer. A roll-over of the count value in TL2/TH2 from all 1’s to all 0’s sets the timer overflow flag ...
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Timer 2 Compare Modes The compare function of a timer/register combination operates as follows: the 16-bit value stored in a compare or compare/capture register is compared with the contents of the timer register; if the count value in the timer ...
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Compare Mode 1 If compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the new value will not appear at the output pin until the next compare match occurs. Thus, it can ...
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Serial Interface (USART) The serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in Table 8 USART Operating Modes SCON Mode SM0 SM1 ...
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Timer 1 Overflow Baud Rate Generator f OSC (SRELH SRELL) ÷ 6 Note: The switch configuration shows the reset state. Figure 15 Block Diagram of Baud Rate Generation for the Serial Interface Table 9 below lists the values/formulas for the ...
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SSC Interface The C515C microcontroller provides a Synchronous Serial Channel unit, the SSC. This interface is compatible to the popular SPI serial bus interface. diagram of the SSC. The central element of the SSC is an 8-bit shift register. The ...
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CAN Controller The on-chip CAN controller is the functional heart which provides all resources that are required to run the standard CAN protocol (11-bit identifiers) as well as the extended CAN protocol (29-bit identifiers). It provides a sophisticated object layer ...
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Messages Handlers Status + Control to internal Bus Figure 17 CAN Controller Block Diagram The TX/RX Shift Register holds the destuffed bit stream from the bus line to allow the parallel access to the whole data or remote frame for ...
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The Cyclic Redundancy Check Register (CRC) generates the Cyclic Redundancy Check code to be transmitted after the data bytes and checks the CRC code of incoming messages. This is done by dividing the data stream by the code generator polynomial. ...
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A/D Converter The C515C includes a high performance / high speed 10-bit A/D-Converter (ADC) with 8 analog input channels. It operates with a successive approximation technique and uses self calibration mechanisms for reduction and compensation of offset and linearity ...
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OSC ÷ Clock Prescaler Conditions: MCU System Clock Rate OSC 2 MHz 4 MHz 6 MHz 8 MHz 10 MHz Figure 18 A/D Converter Clock Selection Data Sheet ADCL 4 Conversion Clock f MUX 8 ...
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IEN1 ( EXEN2 IRCON (C0 ) EXF2 P6 (DB ) P6.7 ADCON1 (DC ) ADCL ADCON0 ( Port 6 Conversion f Clock OSC Prescaler V AREF V AGND P4.0/ADST Write to ADDATL Shaded bit locations are ...
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Interrupt System The C515C provides 17 interrupt sources with four priority levels. Seven interrupts can be generated by the on-chip peripherals (timer 0, timer 1, timer 2, serial interface, A/D converter, SSC interface, CAN controller), and ten interrupts may be ...
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P3.2/ INT0 IT0 TCON.0 A/D Converter Timer 0 Overflow Status SIE < CR.2 Error EIE CR.3 Message Transmit TXIE _ 1 < MCR0.3/2 Message Receive RXIE MCR0.5/4 P1.4/ INT2 I2FR T2CON.5 Bit addressable Request Flag is cleared by ...
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P3.3/ INT1 IT1 TCON.2 WCOL WCEN SCF.1 SSC SCIEN.1 Inerface TC TCEN SCF.0 SCIEN.0 P1.0/ INT3/ CC0 I3FR T2CON.6 Timer 1 Overflow P1.1/ INT4/ CC1 Bit addressable Request Flag is cleared by hardware Figure 21 Interrupt Request Sources (Part 2) ...
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RI SCON.0 USART TI SCON.1 P7.0/ INT7 P1.2/ INT5/ CC2 Timer 2 TF2 Overflow IRCON.6 P1.5/ EXF2 T2EX IRCON.7 EXEN2 IEN1.7 P4.5/ INT8 P1.3/ INT6/ CC3 Bit addressable Request Flag is cleared by hardware Figure 22 Interrupt Request Sources (Part ...
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Table 10 Interrupt Source and Vectors Interrupt Source External Interrupt 0 Timer 0 Overflow External Interrupt 1 Timer 1 Overflow Serial Channel Timer 2 Overflow / Ext. Reload 002B A/D Converter External Interrupt 2 External Interrupt 3 External Interrupt 4 ...
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... Fail Save Mechanisms The C515C offers two on-chip peripherals which monitor the program flow and ensure an automatic “fail-safe” reaction for cases where the controller’s hardware fails or the software hangs up: • A programmable watchdog timer (WDT) with variable time-out period from 512 microseconds up to approx. 1.1 seconds at 6 MHz. • ...
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WDT and SWDT each. The reset cause (external reset or reset caused by the watchdog) can be examined by software (flag WDTS). It must be noted, however, that the watchdog timer is halted ...
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EWPD (PCON1.7) Control P3.2/ Logic INT0 Start/ Stop RC f Oscillator RC 3 MHz Start/ Stop XTAL1 On-Chip Oscillator XTAL2 Figure 24 Block Diagram of the Oscillator Watchdog Data Sheet Power-Down Mode Activated f 1 ÷2 ÷5 f < Frequency ...
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Power Saving Modes The C515C provides two basic power saving modes, the idle mode and the power down mode. Additionally, a slow down mode is available. This power saving mode reduces the internal clock rate in normal operating mode and ...
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Table 11 Power Saving Modes Overview Mode Entering (2-Instruction Example) Idle mode ORL PCON, #01 ORL PCON, #20 Software ORL PCON, #02 Power-Down ORL PCON, #40 Mode Hardware HWPD = low Power-Down Mode Slow Down ORL PCON, #10 Mode Data ...
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OTP Memory Operation (C515C-8E only) The C515C-8E contains a 64 Kbytes one-time programmable (OTP) program memory. With the C515C-8E fast programming cycles are achieved (1 byte in 100 s). Also several levels of OTP memory protection can be selected. For ...
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C515C-8E Pin Configuration in Programming Mode N.C. 62 N.C. 63 N.C. 64 N.C. 65 N.C. 66 N. N.C. 72 N.C. 73 N.C. 74 N.C. 75 N.C. ...
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The following Table 12 contains the functional description of all C515C-8E pins which are required for OTP memory programming. Table 12 Pin Definitions and Functions in Programming Mode Symbol Pin Number I/O RESET 1 PMSEL0 15 PMSEL1 16 PSEL 17 ...
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Table 12 Pin Definitions and Functions in Programming Mode (cont’d) Symbol Pin Number I/O A0/ A7/A15 PSEN 47 PROG 13, 34, 35, SS 51, ...
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C515C-8E Basic Programming Mode Selection The basic programming mode selection scheme is shown Clock (XTAL1/XTAL2) RESET PSEN PMSEL1, 0 PROG PRD PSEL PALE EA Figure 27 C515C-8E Basic Programming Mode Selection Data Sheet Stable "0" ...
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Table 13 Access Modes Selection Access Mode Program OTP memory byte Read OTP memory byte Program OTP lock bits Read OTP lock bits Read OTP version byte C515C-8E Lock Bits Programming / Read The C515C-8E has two programmable lock bits ...
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Table 14 Lock Bit Protection Types Lock Bits at Protection D1, D0 Level Level Level Level Level 3 Data Sheet Protection Type The OTP lock feature is ...
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Absolute Maximum Ratings Parameter Storage temperature V Voltage on pins with DD V respect to ground ( ) SS Voltage on any pin with respect V to ground ( ) SS Input current on any pin during overload condition Absolute ...
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... Operating Conditions Parameter Supply voltage Ground voltage Ambient temperature: SAB-C515C SAF-C505 SAH-C505 Analog reference voltage Analog ground voltage Analog input voltage XTAL clock Data Sheet Symbol Limit Values min. max. V 4. -40 110 AREF 0.1 AGND AIN AGND AREF OSC 66 Unit Notes ...
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DC Characteristics (Operating Conditions apply) Parameter Input low voltages all except EA, RESET, HWPD EA pin RESET and HWPD pins Port 5 in CMOS mode Input high voltages all except XTAL2, RESET, and HWPD) XTAL2 pin RESET and HWPD pins ...
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Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these ...
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Power Supply Current Parameter Active mode C515C-8R/ C515C-LM C515C-8E Idle mode C515C-8R/ C515C-LM C515C-8E Active mode C515C-8R/ with slow-down C515C-LM enabled C515C-8E Idle mode with C515C-8R/ slow-down C515C-LM enabled C515C-8E Power-down C515C-8R/ mode C515C-LM C515C- EA/ in C515C-8E ...
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I (idle mode with slow-down mode) is measured with all output pins disconnected and with all peripherals DD disabled XTAL2 driven with , CLCH CHCL RESET = Port0 = DD SS ...
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Power Supply Current Calculation Formulas Parameter Active mode Idle mode Active mode with slow-down enabled Idle mode with slow-down enabled f Note: is the oscillator frequency in MHz. OSC Data Sheet Symbol I C515C-8R/ DD typ I C515C-LM DD max ...
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I Figure 28 Diagrams of C515C-8R/C515C-LM DD Data Sheet C515C C515C-8E C515C- max I DD typ f OSC [MHz] 10 2003-02 ...
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I Figure 29 Diagrams of C515C-8E DD Data Sheet C515C C515C- max I DD typ f OSC [MHz] 10 2003-02 ...
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A/D Converter Characteristics (Operating Conditions apply) Parameter Analog input voltage Sample time Conversion cycle time Total unadjusted error Internal resistance of reference voltage source Internal resistance of analog source ADC input capacitance may exceed or AIN AGND ...
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Clock Calculation Table Clock Prescaler Ratio 8 4 Further timing conditions: Data Sheet t ADCL ADC 500 ns ADC min OSC CLP ...
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AC Characteristics (Operating Conditions apply for port 0, ALE and PSEN outputs = 100 pF; L Program Memory Characteristics Parameter Symbol t ALE pulse width t Address setup to ALE t Address hold after ALE t ALE to ...
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External Data Memory Characteristics Parameter Symbol t RD pulse width RLRH t WR pulse width WLWH t Address hold after LLAX2 ALE valid data in RLDV t Data hold after RD RHDX t Data float after RD ...
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SSC Interface Characteristics Parameter Clock Cycle Time: Master Mode Slave Mode Clock high time Clock low time Data output delay Data output hold Data input setup Data input hold TC bit set delay External Clock Drive at XTAL2 Parameter Symbol ...
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ALE PSEN Port 0 Port 2 Figure 30 Program Memory Read Cycle Data Sheet t LHLL t t AVLL PLPH t LLPL t LLIV t PLIV t AZPL t LLAX Instr.IN t AVIV A8 - A15 79 ...
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ALE PSEN RD t AVLL from Port DPL t AVWL Port 2 Figure 31 Data Memory Read Cycle Data Sheet t LLDV t t LLWL RLRH t RLDV LLAX2 t RLAZ Data IN ...
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ALE PSEN WR t AVLL from Port DPL t AVWL Port 2 Figure 32 Data Memory Write Cycle XTAL2 Figure 33 External Clock Drive at XTAL2 Data Sheet t t LLWL WLWH t ...
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SCLK t SCL SCLK t D STO SRI MSB TC Figure 34 SSC Timing Notes: 1. Shown is the data/clock relationship for CPOL = CPHA = 1. The timing diagram is valid for the other cases ...
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OTP Memory Programming Mode Characteristics 10 Parameter ALE pulse width PMSEL setup to ALE rising edge Address setup to ALE, PROG, or PRD falling edge Address hold after ALE, PROG, ...
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PAW PALE t PMS PMSEL1,0 t Port 2 Port 0 PROG Notes: PRD must be high during a programming write cycle. Figure 35 Programming Code Byte - Write Cycle Timing Data Sheet PAS PAH A8-15 t ...
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PAW PALE t PMS PMSEL1,0 t Port 2 Port 0 PRD Notes: PROG must be high during a programming read cycle. Figure 36 Verify Code Byte - Read Cycle Timing Data Sheet PAS PAH A8-15 t ...
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PMSEL1,0 Port 0 t PMS PROG PRD Note: PALE should be low during a lock bit read / write cycle. Figure 37 Lock Bit Access Timing Data Sheet PCH PCS t PMH t t ...
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PMSEL1,0 Port 2 Port 0 PRD Note: Figure 38 Version Byte - Read Timing Data Sheet D0-7 t PCS t PRD t PMS t PRW PROG must be high during a programming read cycle. ...
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ROM/OTP Verification Characteristics for C515C-8R / C515C-8E ROM Verification Mode 1 (C515C-8R) Parameter Address to valid data P1.0 - P1.7 P2.0 - P2.7 Port 0 Data: Addresses: Figure 39 ROM Verification Mode 1 Data Sheet Symbol t AVQV Address t ...
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ROM/OTP Verification Mode 2 Parameter ALE pulse width ALE period Data valid after ALE Data stable after ALE P3.5 setup to ALE low Oscillator frequency ALE Port 0 P3.5 Figure 40 ROM/OTP Verification Mode 2 Data Sheet Symbol min. t ...
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Inputs during testing are driven at Timing measurements are made at Figure 41 AC Testing: Input, Output Waveforms V +0.1 V Load V Load V Load For timing purposes a port pin ...
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Package Outlines P-MQFP-80-1 (Plastic Metric Quad Flat Package) 0.65 0.3 ±0. Index Marking 1) Does not include plastic or metal protrusions of 0.25 max per side You can find all of our packages, sorts of packing and ...
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