SAF-XE167F-96F66L AC Infineon Technologies, SAF-XE167F-96F66L AC Datasheet
SAF-XE167F-96F66L AC
Specifications of SAF-XE167F-96F66L AC
SAF-XE167F-96F66LACIN
SP000363803
Related parts for SAF-XE167F-96F66L AC
SAF-XE167F-96F66L AC Summary of contents
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XE167 ...
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... Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life ...
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XE167 ...
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XE167 Revision History: V2.1, 2008-08 Previous Version(s): V2.0, 2008-03, Preliminary V0.1, 2007-09, Preliminary Page Subjects (major changes since last revision) several Maximum frequency changed to 80 MHz 33 Voltage domain for XTAL1/XTAL2 corrected Coupling factors corrected 78, ...
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Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Single-Chip Real Time Signal Controller XE166 Family 1 Summary of Features For a quick overview and easy reference, the features of the XE167 are summarized here. • High-performance CPU with five-stage pipeline – 12.5 ns instruction cycle at 80 ...
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serial interface channels to be used as UART, LIN, high-speed synchronous channel (SPI/QSPI), IIC bus interface (10-bit addressing, 400 kbit/s), IIS interface – On-chip MultiCAN interface (Rev. 2.0B active) with up to 128 message objects (Full ...
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... SAF-XE167G- -40 ° °C 72F66L SAF-XE167G- -40 ° °C 96F66L SAF-XE167H- -40 ° °C 48F66L SAF-XE167H- -40 ° °C 72F66L SAF-XE167H- -40 ° °C 96F66L SAF-XE167K- -40 ° °C 48F66L SAF-XE167K- -40 ° °C 72F66L SAF-XE167K- -40 ° °C 96F66L 1) This Data Sheet is valid for devices starting with and including design step AC. ...
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The XE167 types are offered with several Flash memory sizes. location of the available memory areas for each Flash memory size. Table 2 Flash Memory Allocation Total Flash Size 768 Kbytes 576 Kbytes 384 Kbytes 1) The uppermost 4-Kbyte sector ...
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General Device Information The XE167 series of real time signal controllers is a part of the Infineon XE166 Family of full-feature single-chip CMOS microcontrollers. These devices extend the functionality and performance of the C166 Family in terms of instructions ...
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Pin Configuration and Definition The pins of the XE167 are described in detail in functions. For further explanations please refer to the footnotes at the end of the table. Figure 2 summarizes all pins, showing their locations on the ...
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Notes to Pin Definitions 1. Ctrl.: The output signal for a port pin is selected by bitfield PC in the associated register Px_IOCRy. Output O0 is selected by setting the respective bitfield PC to 1x00 , output O1 is selected ...
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Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B T3OUT O1 T6OUT O2 TDO_A OH ESR2_1 I RxDC4B St/B EMUX1 O1 U0C1_DOUT O2 U0C0_DOUT O3 CCU62_ I ...
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Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B EMUX2 O1 U0C1_DOUT O2 U0C1_ O3 SCLKOUT CCU62_ I CCPOS2A TCK_C I U0C0_DX0D I U0C1_DX1E St/B CCU60_ O1 ...
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Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/A EMUX2 O1 T6OUT O2 U1C1_ O3 SCLKOUT U1C1_DX1C St/A T3OUT O2 U1C1_ O3 SELO0 U1C1_DX2D I ADCx_ I ...
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Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 28 P15.7 I ADC1_CH7 AREF1 AREF0 AGND 32 P5.0 I ADC0_CH0 I 33 P5.1 I ADC0_CH1 I 34 P5.2 I ...
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Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 43 P5.8 I ADC0_CH8 I CCU6x_ I T12HRC CCU6x_ I T13HRC 44 P5.9 I ADC0_CH9 I CC2_T7IN I 45 P5.10 I ADC0_CH10 I BRKIN_A I 46 P5.11 I ADC0_CH11 I ...
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Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 52 P2. St/B U0C0_ O1 SELO2 U0C1_ O2 SELO2 BHE/WRH OH 53 P11 St St/B CCU63_ ...
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Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B CC2_24 St/B CS0 St/B U0C0_DOUT O1 CCU63_ O2 COUT63 CC2_16 St/B A16 ...
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Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 66 P11 St/B CCU63_ I CCPOS0A 67 P2 St/B U0C0_ O1 SCLKOUT TxDC0 O2 CC2_18 St/B A18 OH U0C0_DX1D I 68 ...
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Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B CC2_27 St/B CS3 OH RxDC2A I T2EUD St/B U1C0_DOUT O1 CCU61_ St/B ...
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Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B U1C0_DOUT O1 TxDC0 O2 CCU61_ St/B CC61 A1 OH U1C0_DX0B I U1C0_DX1A DP/B Bit 8 ...
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Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B U1C0_ O1 SCLKOUT TxDC0 O2 CCU61_ St/B CC62 A2 OH U1C0_DX1B I 84 P10 St/B U0C1_DOUT O1 CCU60_ ...
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Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B U1C0_ O1 SELO0 U1C1_ O2 SELO1 CCU61_ O3 COUT60 A3 OH U1C0_DX2A I RxDC0B St/B U2C0_DOUT O1 TxDC3 ...
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Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 92 TRef St/B U2C0_ O1 SCLKOUT TxDC3 O2 U2C0_DX1B I HOLD I 94 P2. St/B U0C1_DOUT O1 U0C0_ O2 SELO3 CC2_23 ...
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Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B U2C0_ O1 SELO0 U2C1_ O2 SELO1 U2C0_DX2A I RxDC3A I 98 P10 St/B U0C0_ O1 SELO3 CCU60_ O2 COUT61 AD4 OH ...
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Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 101 P3 St/B U2C1_ O1 SCLKOUT U2C0_ O2 SELO2 U0C0_ O3 SELO5 U2C1_DX1A I 102 P0 St/B U1C1_DOUT O1 TxDC1 O2 CCU61_ O3 COUT63 ...
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Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 104 P3 St/B U2C1_DOUT O1 TxDC4 O2 U0C0_ O3 SELO6 U2C1_DX0A I U2C1_DX1B I 105 P10 St/B U0C1_DOUT O1 CCU60_ O2 COUT63 AD7 OH ...
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Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 111 P1 St/B U1C0_ O1 MCLKOUT U1C0_ O2 SELO4 A8 OH ESR1_3 I EX0BINA I CCU62_ I CTRAPB 112 P9 St/B CCU63_ O1 / ...
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Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 115 P10 St/B U0C0_ O1 SELO4 U0C1_ O2 MCLKOUT AD9 St/B CCU60_ I CCPOS2A TCK_B I 116 P1 St/B CCU62_ O1 ...
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Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 118 P10. St/B U1C0_ O1 SCLKOUT BRKOUT O2 AD11 St/B U1C0_DX1D I RxDC2B I TMS_B I 119 P9 St/B CCU63_ O1 ...
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Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 122 P9 St/B CCU63_ O1 COUT60 BRKOUT O2 123 P10. St/B U1C0_DOUT O1 TxDC3 O2 U1C0_ O3 SELO3 WR/WRL OH U1C0_DX0D I 124 P1.3 ...
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Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 126 P9 St/B CCU63_ O1 COUT62 U2C0_DOUT O2 U2C0_DX0E I CCU60_ I CCPOS2B 128 P10. St/B U1C0_ O1 SELO1 U0C1_DOUT ESR2_2 ...
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Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 131 P1 St/B CCU62_ O1 COUT60 U1C1_ O2 SELO3 BRKOUT O3 A13 OH U2C0_DX0C I 132 P9 St/B CCU63_ O1 COUT63 CCU63_ O2 COUT62 ...
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... Power On Reset Input A low level at this pin resets the XE167 completely. A spike filter suppresses input pulses <10 ns. Input pulses >100 ns safely pass the filter. The minimum duration for a safe recognition should be 120 ns. An internal pullup device will hold this pin high when nothing is driving it ...
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Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 140 ESR2 St/B U1C1_DX0D I U1C1_DX2C I U2C1_DX0E I U2C1_DX2B I EX1AINB I 141 ESR0 St/B U1C0_DX0E I U1C0_DX2B I 142 P8 ...
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Table 4 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl DDPB 36, 38, 72, 74, 108, 110, 144 37, 73, 109 1) To generate the reference clock output for bus timing measurement, EXTCLK ...
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Functional Description The architecture of the XE167 combines advantages of RISC, CISC, and DSP processors with an advanced peripheral subsystem in a well-balanced design. On-chip memory blocks allow the design of compact systems-on-silicon with maximum performance suited for computing, ...
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Memory Subsystem and Organization The memory space of the XE167 is configured in the von Neumann architecture. In this architecture all internal and external resources, including code memory, data memory, registers and I/O ports, are organized in the same ...
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This common memory space consists of 16 Mbytes organized as 256 segments of 64 Kbytes; each segment contains four data pages of 16 Kbytes. The entire memory space can be accessed bytewise or wordwise. Portions of the on-chip DPRAM and ...
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Special Function Register areas (SFR space and ESFR space). SFRs are word-wide registers which are used to control and monitor functions of the different on-chip units. ...
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External Bus Controller All external memory access operations are performed by a special on-chip External Bus Controller (EBC). The EBC also controls access to resources connected to the on-chip LXBus (MultiCAN and the USIC modules). The LXBus is an ...
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Central Processing Unit (CPU) The core of the CPU consists of a 5-stage execution pipeline with a 2-stage instruction- fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply and accumulate unit (MAC), a register-file providing three ...
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With this hardware most XE167 instructions can be executed in a single machine cycle of 12.5 ns with an 80-MHz CPU clock. For example, shift and rotate instructions are always processed during one machine cycle, no matter how many bits ...
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Interrupt System With a minimum interrupt response time of 7/11 program execution), the XE167 can react quickly to the occurrence of non-deterministic events. The architecture of the XE167 supports several mechanisms for fast and flexible response to service requests; ...
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Table 6 XE167 Interrupt Nodes Source of Interrupt or PEC Service Request CAPCOM Register 16, or ERU Request 0 CAPCOM Register 17, or ERU Request 1 CAPCOM Register 18, or ERU Request 2 CAPCOM Register 19, or ERU Request 3 ...
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Table 6 XE167 Interrupt Nodes (cont’d) Source of Interrupt or PEC Service Request GPT2 Timer 5 GPT2 Timer 6 GPT2 CAPREL Register CAPCOM Timer 7 CAPCOM Timer 8 A/D Converter Request 0 A/D Converter Request 1 A/D Converter Request 2 ...
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Table 6 XE167 Interrupt Nodes (cont’d) Source of Interrupt or PEC Service Request CAN Request 1 CAN Request 2 CAN Request 3 CAN Request 4 CAN Request 5 CAN Request 6 CAN Request 7 CAN Request 8 CAN Request 9 ...
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Table 6 XE167 Interrupt Nodes (cont’d) Source of Interrupt or PEC Service Request USIC2 Cannel 1, Request 0 USIC2 Cannel 1, Request 1 USIC2 Cannel 1, Request 2 Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node ...
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The XE167 includes an excellent mechanism to identify and process exceptions or error conditions that arise during run-time, the so-called ‘Hardware Traps’. A hardware trap causes an immediate non-maskable system reaction similar to a standard interrupt service (branching to a ...
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On-Chip Debug Support (OCDS) The On-Chip Debug Support system built into the XE167 provides a broad range of debug and emulation features. User software running on the XE167 can be debugged within the target system environment. The OCDS is ...
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Capture/Compare Unit (CAPCOM2) The CAPCOM2 unit supports generation and control of timing sequences channels with a maximum resolution of one system clock cycle (eight cycles in staggered mode). The CAPCOM2 unit is typically used to ...
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When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (‘captured’) into the capture/compare register in response to an external event at the port pin associated with this register. In ...
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CC T7IN T6OUF CC16IO CC17IO CC31IO f CC T6OUF Figure 5 CAPCOM2 Unit Block Diagram Data Sheet Reload Reg . T7 Input Timer T7 Control Mode Sixteen Control (Capture Capture/ or Compare Compare) Registers T8 Input Timer T8 Control ...
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Capture/Compare Units CCU6x The XE167 features up to four CCU6 units (CCU60, CCU61, CCU62, CCU63). The CCU6 is a high-resolution capture and compare unit with application-specific modes. It provides inputs to start the timers synchronously, an important feature in ...
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SYS TxHR T12 Interrupts st art T13 Figure 6 CCU6 Block Diagram Timer T12 can work in capture and/or compare mode for its three channels. The modes can also be combined. Timer T13 can work in compare mode only. ...
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General Purpose Timer (GPT12E) Unit The GPT12E unit is a very flexible multifunctional timer/counter structure which can be used for many different timing tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or ...
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T3CON.BPS1 GPT T2IN T2 Mode Control T2EUD T3 T3IN Mode Control T3EUD T4IN T4 Mode Control T4EUD Figure 7 Block Diagram of GPT1 Data Sheet XE166 Family Derivatives Basic Clock Aux. Timer T2 U/D Reload Capture ...
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With its maximum resolution of 2 system clock cycles, the GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which ...
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T6CON.BPS2 GPT T5IN Mode T5EUD Control CAPIN CAPREL Mode Control T3IN/ T3EUD Mode T6IN Control T6EUD Figure 8 Block Diagram of GPT2 Data Sheet Basic Clock GPT2 Timer T5 T5 U/D Clear Capture GPT2 CAPREL Reload ...
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Real Time Clock The Real Time Clock (RTC) module of the XE167 can be clocked with a clock signal selected from internal sources or external sources (pins). The RTC basically consists of a chain of divider blocks: • Selectable ...
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The RTC module can be used for different purposes: • System clock to determine the current time and date • Cyclic time-based interrupt, to provide a system time tick independent of CPU frequency and other resources • 48-bit timer for ...
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A/D Converters For analog signal measurement two 10-bit A/D converters (ADC0, ADC1) with multiplexed input channels and a sample and hold circuit have been integrated on-chip. They use the successive approximation method. The sample ...
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Universal Serial Interface Channel Modules (USIC) The XE167 includes up to three USIC modules (USIC0, USIC1, USIC2), each providing two serial communication channels. The Universal Serial Interface Channel (USIC) module is based on a generic data shift and data ...
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Target Protocols Each USIC channel can receive and transmit data frames with a selectable data word width from bits in each of the following protocols: • UART (asynchronous serial channel) – maximum baud rate: – data frame ...
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MultiCAN Module The MultiCAN module contains up to five independently operating CAN nodes with Full- CAN functionality which are able to exchange Data and Remote Frames using a gateway function. Transmission and reception of CAN frames is handled in ...
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MultiCAN Features • CAN functionality conforming to CAN specification V2.0 B active for each CAN node (compliant to ISO 11898) • five independent CAN nodes • 128 independent message objects (shared by the CAN nodes) • Dedicated control ...
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... Watchdog Timer The Watchdog Timer is one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after an application reset of the chip. It can be disabled and enabled at any time by executing the instructions DISWDT and ENWDT respectively ...
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Parallel Ports The XE167 provides up to 118 I/O lines which are organized into 11 input/output ports and 2 input ports. All port lines are bit-addressable, and all input/output lines can be individually (bit-wise) configured via port control registers. ...
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Table 9 Summary of the XE167’s Parallel Ports (cont’d) Port Width Alternate Functions Port 5 16 Analog input channels to ADC0, Input/Output lines for CCU6x, Timer control signals, JTAG, OCDS control, interrupts Port 6 4 ADC control lines, Serial interface ...
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Instruction Set Summary Table 10 lists the instructions of the XE167. The addressing modes that can be used with a specific instruction, the function of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction ...
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Table 10 Instruction Set Summary (cont’d) Mnemonic Description ROL/ROR Rotate left/right direct word GPR ASHR Arithmetic (sign bit) shift right direct word GPR MOV(B) Move word (byte) data MOVBS/Z Move byte operand to word op. with sign/zero extension JMPA/I/R Jump ...
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Table 10 Instruction Set Summary (cont’d) Mnemonic Description NOP Null operation CoMUL/CoMAC Multiply (and accumulate) CoADD/CoSUB Add/Subtract Co(A)SHR (Arithmetic) Shift right CoSHL Shift left CoLOAD/STORE Load accumulator/Store MAC register CoCMP Compare CoMAX/MIN Maximum/Minimum CoABS/CoRND Absolute value/Round accumulator CoMOV Data move ...
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Electrical Parameters The operating range for the XE167 is defined by its electrical parameters. For proper operation the specified limits must be respected during system design. Note: Typical parameter values refer to room temperature and nominal supply voltage, minimum/maximum ...
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Operating Conditions The following operating conditions must not be exceeded to ensure correct operation of the XE167. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Table 12 Operating Condition Parameters Parameter Digital core ...
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Table 12 Operating Condition Parameters (cont’d) Parameter External Pin Load Capacitance Voltage Regulator Buffer Capacitance for DMP_M Voltage Regulator Buffer Capacitance for DMP_1 Operating frequency Ambient temperature 1) If both core power domains are clocked, the difference between the power ...
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Parameter Interpretation The parameters listed in the following include both the characteristics of the XE167 and its demands on the system. To aid in correctly interpreting the parameters when evaluating them for a design, they are marked accordingly in the ...
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DC Parameters These parameters are static or average values that may be exceeded during switching transitions (e.g. output current). The XE167 can operate within a wide supply voltage range from 3 5.5 V. However, during operation this ...
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Pullup/Pulldown Device Behavior Most pins of the XE167 feature pullup or pulldown devices. For some special pins these are fixed; for the port pins they can be selected by the application. The specified current values indicate how to load the ...
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DC Parameters for Upper Voltage Area These parameters apply to the upper IO voltage range, 4.5 V ≤ Table 14 DC Characteristics for Upper Voltage Range (Operating Conditions apply) Parameter Input low voltage (all except XTAL1) Input high voltage ...
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As a rule, with decreasing output current the output levels approach the respective supply level ( → However, only the levels for nominal output currents are verified. OH DDP 5) This specification is not valid for ...
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DC Parameters for Lower Voltage Area These parameters apply to the lower IO voltage range, 3.0 V ≤ Table 15 DC Characteristics for Lower Voltage Range (Operating Conditions apply) Parameter Input low voltage (all except XTAL1) Input high voltage ...
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As a rule, with decreasing output current the output levels approach the respective supply level ( → However, only the levels for nominal output currents are verified. OH DDP 5) This specification is not valid for ...
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Power Consumption The power consumed by the XE167 depends on several factors such as supply voltage, operating frequency, active circuits, and operating temperature. The power consumption specified here consists of two components: • The switching current I • The ...
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Table 16 Switching Power Consumption XE167 (Operating Conditions apply) Parameter Power supply current (active) with all peripherals active and EVVRs on Power supply current in stopover mode, EVVRs on 1) The pad supply voltage pins ( by the pin output ...
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I [mA] S 100 Figure 13 Supply Current in Active Mode as a Function of Frequency Data Sheet XE166 Family Derivatives XE167x Electrical Parameters I SACTmax I ...
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Table 17 Leakage Power Consumption XE167 (Operating Conditions apply) Parameter 2) Leakage supply current 3) -α : 600,000 × e Formula ; α = 5000 / (273 + B× Typ 1.0, Max 1.3 ...
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Analog/Digital Converter Parameters These parameters describe the conditions for optimum ADC performance. Table 18 A/D Converter Characteristics (Operating Conditions apply) Parameter Analog reference supply Analog reference ground Analog input voltage range Analog clock frequency Conversion time for 10-bit 4) ...
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Table 18 A/D Converter Characteristics (cont’d) (Operating Conditions apply) Parameter Switched capacitance of the reference input Resistance of the reference input path TUE is tested at = AREFx DDPA voltage range. The specified TUE is valid only ...
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Sample time and conversion time of the XE167’s A/D converters are programmable. The timing above can be calculated using f The limit values for must not be exceeded when selecting the prescaler value. ADCI Table 19 A/D Converter Computation Table ...
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System Parameters The following parameters specify several aspects which are important when integrating the XE167 into an application system. Note: These parameters are not subject to production test but verified by design and/or characterization. Table 20 Various System Parameters ...
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Table 21 Coding of Bitfields LEVxV in Register SWDCON0 Code Default Voltage Level 0000 2 0001 3 0010 3 0011 3 0100 3 0101 3 0110 3.6 V ...
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Flash Memory Parameters The XE167 is delivered with all Flash sectors erased and with no protection installed. The data retention time of the XE167’s Flash memory (i.e. the time after which stored data can still be retrieved) depends on ...
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Table 24 Flash Access Waitstates Required Waitstates 4 WS (WSFLASH = 100 (WSFLASH = 011 (WSFLASH = 010 (WSFLASH = 001 (WSFLASH = 000 B Note: The maximum ...
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AC Parameters These parameters describe the dynamic behavior of the XE167. 4.6.1 Testing Waveforms These values are used for characterization and production testing (except pin XTAL1). Output delay Hold time 0.8 V DDP 0.7 V DDP 0.3 V DDP ...
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Definition of Internal Timing The internal operation of the XE167 is controlled by the internal system clock Because the system clock signal external sources using different mechanisms, the duration of the system clock periods (TCSs) and their variation (as ...
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Direct Drive When direct drive operation is selected (SYSCON0.CLKSEL = 11 derived directly from the input clock signal CLKIN1 SYS IN f The frequency of is the same as the frequency of SYS f times of ...
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The timing in the AC Characteristics refers to TCSs. Timing must be calculated using the minimum TCS possible under the given circumstances. The actual minimum value for TCS depends on the jitter of the PLL. Because the PLL is constantly ...
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D Acc. jitter T ns ±9 ±8 ±7 ±6 ±5 ±4 ±3 ±2 ± Figure 19 Approximated Accumulated PLL Jitter Note: The specified PLL jitter values are valid if the capacitive load per pin does not C ...
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Wakeup Clock When wakeup operation is selected (SYSCON0.CLKSEL = 00 derived from the low-frequency wakeup clock source SYS WU In this mode, a basic functionality can be maintained without requiring an external clock source and while ...
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External Clock Input Parameters These parameters specify the external clock generation for the XE167. The clock can be generated in two ways: • By connecting a crystal or ceramic resonator to pins XTAL1/XTAL2. • By supplying an external clock ...
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V OFF Figure 20 External Clock Drive XTAL1 Note: For crystal/resonator operation strongly recommended to measure the oscillation allowance (negative resistance) in the final target system (layout) to determine the optimum parameters for oscillator operation. Please refer to ...
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External Bus Timing The following parameters specify the behavior of the XE167 bus interface. Table 27 CLKOUT Reference Signal Parameter CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time 1) The CLKOUT cycle ...
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Variable Memory Cycles External bus cycles of the XE167 are executed in five consecutive cycle phases (AB F). The duration of each cycle phase is programmable (via the TCONCSx registers) to adapt the external bus cycles to ...
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Table 29 External Bus Cycle Timing for Upper Voltage Range (Operating Conditions apply) Parameter Output valid delay for: RD, WR(L/H) Output valid delay for: BHE, ALE Output valid delay for: A23 … A16, A15 … A0 (on P0/P1) Output valid ...
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Table 30 External Bus Cycle Timing for Lower Voltage Range (Operating Conditions apply) Parameter Output valid delay for: RD, WR(L/H) Output valid delay for: BHE, ALE Output valid delay for: A23 … A16, A15 … A0 (on P0/P1) Output valid ...
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CLKOUT t 11 ALE A23-A16, BHE, CSx RD WR(L/H) t AD15-AD0 (read) t AD15-AD0 (write) Figure 22 Multiplexed Bus Cycle Data Sheet High Address ...
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AB CLKOUT t 11 ALE A23-A0, BHE, CSx RD WR(L/H) D15-D0 (read) D15-D0 (write) Figure 23 Demultiplexed Bus Cycle Data Sheet Address 106 XE167x ...
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... An asynchronous READY signal puts no timing constraints on the input signal but incurs a minimum of one waitstate due to the additional synchronization stage. The minimum duration of an asynchronous READY signal for safe synchronization is one CLKOUT period plus the input setup time. An active READY signal can be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR) ...
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CLKOUT RD, WR D15-D0 (read) D15-D0 (write) READY Synchronous READY Asynchron. Figure 24 READY Timing Note: If the READY input is sampled inactive at the indicated sampling point (“Not Rdy”) a READY-controlled waitstate is inserted (tpRDY), sampling the READY input ...
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External Bus Arbitration If the arbitration signals are enabled, the XE167 makes its external resources available in response to an arbitration request. Table 31 Bus Arbitration Timing for Upper Voltage Range (Operating Conditions apply) Parameter Input setup time for: HOLD ...
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CLKOUT HOLD HLDA BREQ CSx, RD, WR(L/H) Addr, Data, BHE Figure 25 External Bus Arbitration, Releasing the Bus Notes 1. The XE167 completes the currently running bus cycle before granting bus access. 2. This is the first possibility for BREQ ...
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CLKOUT HOLD HLDA BREQ CSx, RD, WR(L/H) Addr, Data, BHE Figure 26 External Bus Arbitration, Regaining the Bus Notes 1. This is the last chance for BREQ to trigger the indicated regain sequence. Even if BREQ is activated earlier, the ...
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Synchronous Serial Interface Timing The following parameters are applicable for a USIC channel operated in SSC mode. Note: These parameters are not subject to production test but verified by design and/or characterization. Table 33 SSC Master/Slave Mode Timing for ...
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Table 34 SSC Master/Slave Mode Timing for Lower Voltage Range (Operating Conditions apply), Parameter Master Mode Timing Slave select output SELO active to first SCLKOUT transmit edge Slave select output SELO inactive after last SCLKOUT receive edge Transmit data output ...
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Master Mode Timing Select Output Inactive SELOx Clock Output SCLKOUT Data Output DOUT Data Input DX0 Slave Mode Timing Select Input Inactive DX2 Clock Input DX1 Data Input DX0 Data Output DOUT Transmit Edge: with this clock edge , transmit ...
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JTAG Interface Timing The following parameters are applicable for communication through the JTAG debug interface. The JTAG module is fully compliant with IEEE1149.1-2000. Note: These parameters are not subject to production test but verified by design and/or characterization. Table ...
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V 0.5 DDP t 2 Figure 28 Test Clock Timing (TCK) TCK TMS TDI t 9 TDO Figure 29 JTAG Timing Data Sheet 116 XE167x XE166 Family Derivatives ...
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Package and Reliability In addition to the electrical parameters, the following specifcations ensure proper integration of the XE167 into the target system. 5.1 Packaging These parameters specify the packaging rather than the silicon. Table 36 Package Parameters (PG-LQFP-144-4) Parameter ...
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Package Outlines 0.5 17.5 2) 0.22 ±0.05 0. 144 1 Index Marking 1) Does not include plastic or metal protrusion of 0.25 max. per side 2) Does not include dambar protrusion of 0.08 max. per ...
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Thermal Considerations When operating the XE167 in a system, the total heat generated in the chip must be dissipated to the ambient environment to prevent overheating and the resulting thermal damage. The maximum heat that can be dissipated depends ...
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