SAK-TC1797-512F180E AC Infineon Technologies, SAK-TC1797-512F180E AC Datasheet - Page 158
SAK-TC1797-512F180E AC
Manufacturer Part Number
SAK-TC1797-512F180E AC
Description
IC MCU 32BIT FLASH 416-BGA
Manufacturer
Infineon Technologies
Series
TC17xxr
Datasheet
1.SAK-TC1797-512F180E_AC.pdf
(190 pages)
Specifications of SAK-TC1797-512F180E AC
Core Processor
TriCore
Core Size
32-Bit
Speed
180MHz
Connectivity
ASC, CAN, EBI/EMI, MLI, MSC, SSC
Peripherals
DMA, POR, WDT
Number Of I /o
219
Program Memory Size
4MB (4M x 8)
Program Memory Type
FLASH
Ram Size
224K x 8
Voltage - Supply (vcc/vdd)
1.42 V ~ 1.58 V
Data Converters
A/D 48x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
416-BGA
Packages
PG-BGA-416
Max Clock Frequency
180.0 MHz
Sram (incl. Cache)
224.0 KByte
Can Nodes
4
A / D Input Lines (incl. Fadc)
48
Program Memory
4.0 MB
For Use With
B158-H8537-G2-X-7600IN - KIT STARTER TC179X FAMILY
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
SP000432392
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4) Applicable for input pins TESTMODE and TRST.
5)
6) Not subject to production test, verified by design / characterization.
7) This parameter includes the delay of the analog spike filter in the PORST pad.
8) The duration of the boot-time is defined between the rising edge of the PORST and the moment when the first
9) The duration of the boot time is defined between the following events:
Figure 26
Data Sheet
TESTMODE
f
user instruction has entered the CPU and its processing starts.
1. Hardware reset: the falling edge of a short ESR0 pulse and the moment when the first user instruction has
entered
SCU_RSTCNTCON.RELSA ×
If the ESR0 pulse is longer than SCU_RSTCNTCON.RELSA ×
the boot time (ESR0 falling edge to first user instruction).
2. Software reset: the moment of starting the software reset and the moment when the first user instruction
has entered the CPU and its processing starts
FPI
HWCFG
PORST
=
VDDP
TRST
ESR0
Pads
VDD
f
CPU
V
D D PPA
/2
the
Power, Pad and Reset Timing
Pad-state undefined
Tri-state or pull device active
As programmed
CPU
t
POA
t
POA
and
t
hd
t
PIP
T
t
POH
its
FPI
t
t
HDH
PI
.
processing
t
PIP
t
PI
154
starts,
t
hd
t
PIP
if
t
POH
t
t
T
HDH
PI
FPI
the
, only the time beyond should be added to
ESR0
t
t
HDH
PI
Electrical Parameters
pulse
t
PI
V
D D
-12%
is
V1.1, 2009-04
shorter
V
TC1797
D D P
V
reset_beh2
D D PPA
-12%
than
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