PIC16LC61-04/SO Microchip Technology, PIC16LC61-04/SO Datasheet - Page 130
![MICRO CTRL LP 1K 4MHZ OTP 18SOIC](/photos/6/76/67656/150-18-soic_sml.jpg)
PIC16LC61-04/SO
Manufacturer Part Number
PIC16LC61-04/SO
Description
MICRO CTRL LP 1K 4MHZ OTP 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheet
1.PIC16LC62A-04SP.pdf
(337 pages)
Specifications of PIC16LC61-04/SO
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
13
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
OTP
Ram Size
36 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
18-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Data Converters
-
Connectivity
-
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PIC16C6X
13.4.5
On power-up the time-out sequence is as follows: First
a PWRT time-out is invoked after the POR time delay
has expired. Then OST is activated. The total time-out
will vary based on oscillator configuration and the sta-
tus of the PWRT. For example, in RC mode, with the
PWRT disabled, there will be no time-out at all.
Figure 13-11, Figure 13-12, and Figure 13-13 depict
time-out sequences on power-up.
Since the time-outs occur from the POR pulse, if the
MCLR/V
will expire. Then bringing the MCLR/V
begin execution immediately (Figure 13-14). This is
useful for testing purposes or to synchronize more than
one PIC16CXX device operating in parallel.
Table 13-10 and Table 13-11 show the reset conditions
for some special function registers, while Table 13-12
shows the reset conditions for all the registers.
TABLE 13-5:
TABLE 13-6:
TABLE 13-7:
TABLE 13-8:
DS30234D-page 130
Legend: x = unknown, u = unchanged
Oscillator Configuration
POR
Oscillator Configuration
TO
0
0
0
1
1
1
1
1
0
0
1
PP
TIME-OUT SEQUENCE
XT, HS, LP
pin is kept low long enough, the time-outs
XT, HS, LP
RC
RC
TIME-OUT IN VARIOUS SITUATIONS, PIC16C61/62/64/65
TIME-OUT IN VARIOUS SITUATIONS,
PIC16C62A/R62/63/R63/64A/R64/65A/R65/66/67
STATUS BITS AND THEIR SIGNIFICANCE, PIC16C61
STATUS BITS AND THEIR SIGNIFICANCE, PIC16C62/64/65
TO
1
0
x
0
0
u
1
PD
1
1
0
0
Power-on Reset or MCLR reset during normal operation
WDT Reset
WDT Wake-up
MCLR reset during SLEEP or interrupt wake-up from SLEEP
PD
1
x
0
1
0
u
0
72 ms + 1024T
PWRTE = 0
PP
72 ms + 1024T
72 ms
Power-on Reset
Illegal, TO is set on a Power-on Reset
Illegal, PD is set on a Power-on Reset
WDT Reset
WDT Wake-up
MCLR reset during normal operation
MCLR reset during SLEEP or interrupt wake-up from SLEEP
pin high will
PWRTE = 1
72 ms
Power-up
OSC
OSC
Power-up
PWRTE = 1
1024T
—
13.4.6
The Power Control/Status Register, PCON has up to
two bits, depending upon the device. Bit0 is not imple-
mented on the PIC16C62/64/65.
Bit0 is BOR (Brown-out Reset Status bit). BOR is
unknown on Power-on Reset. It must then be set by the
user and checked on subsequent resets to see if BOR
cleared, indicating that a brown-out has occurred. The
BOR status bit is a “Don’t Care” and is not necessarily
predictable if the Brown-out Reset circuitry is disabled
(by clearing bit BODEN in the Configuration Word).
Bit1 is POR (Power-on Reset Status bit). It is cleared
on a Power-on Reset and unaffected otherwise. The
user must set this bit following a Power-on Reset.
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
OSC
PWRTE = 0
1024T
POWER CONTROL/STATUS REGISTER
(PCON)
—
72 ms + 1024T
OSC
Brown-out
72 ms
1997 Microchip Technology Inc.
OSC
Wake-up from SLEEP
1024 T
Wake up from
—
1024 T
SLEEP
OSC
—
OSC
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