PIC16C66/JW Microchip Technology, PIC16C66/JW Datasheet - Page 84
![IC MCU OTP 8KX14 PWM 28CDIP](/photos/7/29/72984/150-28-cdip_sml.jpg)
PIC16C66/JW
Manufacturer Part Number
PIC16C66/JW
Description
IC MCU OTP 8KX14 PWM 28CDIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16LC62A-04SP.pdf
(337 pages)
4.PIC16C66-04SO.pdf
(6 pages)
Specifications of PIC16C66/JW
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
14KB (8K x 14)
Program Memory Type
EPROM, UV
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
28-CDIP (0.300", 7.62mm) Window
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
- PIC16F616T-ISL PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC16LC62A-04SP PDF datasheet #3
- PIC16C66-04SO PDF datasheet #4
- Current page: 84 of 337
- Download datasheet (3Mb)
PIC16C6X
11.2
This section contains register definitions and opera-
tional characteristics of the SPI module for the
PIC16C62, PIC16C62A, PIC16CR62, PIC16C63,
PIC16CR63, PIC16C64, PIC16C64A, PIC16CR64,
PIC16C65, PIC16C65A, PIC16CR65.
FIGURE 11-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)
DS30234D-page 84
bit7
bit 7-6: Unimplemented: Read as '0'
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
U-0
—
SPI Mode for PIC16C62/62A/R62/63/
R63/64/64A/R64/65/65A/R65
D/A: Data/Address bit (I
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
P: Stop bit (I
1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET)
0 = Stop bit was not detected last
S: Start bit (I
1 = Indicates that a start bit has been detected last (this bit is '0' on RESET)
0 = Start bit was not detected last
R/W: Read/Write bit information (I
This bit holds the R/W bit information following the last address match. This bit is valid from the address
match to the next start bit, stop bit, or ACK bit.
1 = Read
0 = Write
UA: Update Address (10-bit I
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
BF: Buffer Full Status bit
Receive (SPI and I
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I
1 = Transmit in progress, SSPBUF is full
0 = Transmit complete, SSPBUF is empty
U-0
—
D/A
2
R-0
C mode only)
2
2
C mode only. This bit is cleared when the SSP module is disabled, SSPEN is cleared)
C mode only. This bit is cleared when the SSP module is disabled, SSPEN is cleared)
2
C modes)
R-0
P
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
2
C mode only)
2
C mode only)
R-0
S
2
C mode only)
R/W
R-0
R-0
UA
R-0
BF
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
- n =Value at POR reset
1997 Microchip Technology Inc.
read as ‘0’
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