PIC18C242/JW Microchip Technology, PIC18C242/JW Datasheet - Page 212
PIC18C242/JW
Manufacturer Part Number
PIC18C242/JW
Description
IC MCU EPROM 8KX16 A/D 28CDIP
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C242-ISO.pdf
(305 pages)
4.PIC18C242-ISO.pdf
(12 pages)
Specifications of PIC18C242/JW
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
16KB (8K x 16)
Program Memory Type
EPROM, UV
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
28-CDIP (0.300", 7.62mm) Window
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C242/JW
Manufacturer:
NS
Quantity:
10
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18C242-ISO PDF datasheet #3
- PIC18C242-ISO PDF datasheet #4
- Current page: 212 of 305
- Download datasheet (6Mb)
PIC18CXX2
IORLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39026C-page 210
Q Cycle Activity:
Before Instruction
After Instruction
Decode
WREG
WREG
Q1
=
=
Inclusive OR literal with WREG
[ label ]
0
(WREG) .OR. k
N,Z
The contents of WREG are OR’ed
with the eight-bit literal 'k'. The
result is placed in WREG.
1
1
literal ’k’
IORLW
Read
0000
Q2
0x9A
0xBF
k
255
IORLW k
1001
0x35
Process
Data
Q3
WREG
kkkk
Write to
WREG
Q4
kkkk
IORWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
RESULT =
WREG
RESULT =
WREG
Q1
=
=
register ’f’
Inclusive OR WREG with f
[ label ]
0
d
a
(WREG) .OR. (f)
N,Z
Inclusive OR WREG with register
'f'. If 'd' is 0, the result is placed in
WREG. If 'd' is 1, the result is
placed back in register 'f' (default).
If ’a’ is 0, the Access Bank will be
selected, overriding the BSR value.
If ’a’ = 1, then the bank will be
selected as per the BSR value
(default).
1
1
IORWF
Read
0001
Q2
0x13
0x91
0x13
0x93
f
[0,1]
[0,1]
2001 Microchip Technology Inc.
255
RESULT, 0, 1
IORWF
00da
Process
Data
Q3
ffff
dest
f [,d [,a]
destination
Write to
Q4
ffff
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