ATMEGA103-6AC Atmel, ATMEGA103-6AC Datasheet - Page 46

• Manufacturer Part Number: ATMEGA103-6AC
• Description: IC MCU 128K 6MHZ A/D 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA103-6AC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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ATmega103(L)
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When writing to one of the registers TCNT0, OCR0 or TCCR0, the value is
transferred to a temporary register and latched after two positive edges on TOSC1.
The user should not write a new value before the contents of the temporary register
have been transferred to its destination. Each of the three mentioned registers have
their individual temporary register, which means that e.g., writing to TCNT0 does not
disturb an OCR0 write in progress. To detect that a transfer to the destination
register has taken place, an Asynchronous Status Register (ASSR) has been
implemented.
When entering Power-save mode after having written to TCNT0, OCR0 or TCCR0,
the user must wait until the written register has been updated if Timer/Counter0 is
used to wake up the device. Otherwise, the MCU will go to sleep before the changes
have had any effect. This is extremely important if the Output Compare0 interrupt is
used to wake up the device; Output Compare is disabled during write to OCR0 or
TCNT0. If the write cycle is not finished (i.e., the user goes to sleep before the
OCR0UB bit returns to zero), the device will never get a compare match and the
MCU will not wake up.
If Timer/Counter0 is used to wake up the device from Power-save mode,
precautions must be taken if the user wants to reenter Power-save mode: The
interrupt logic needs one TOSC1 cycle to get reset. If the time between wake-up
and reentering Power-save mode is less than one TOSC1 cycle, the interrupt will not
occur and the device will fail to wake up. If the user is in doubt whether the time
before re-entering Power-save is sufficient, the following algorithm can be used to
ensure that one TOSC1 cycle has elapsed:
1. Write a value to TCCR0, TCNT0 or OCR0.
2. Wait until the corresponding Update Busy Flag in ASSR returns to zero.
3. Enter Power-save mode.
When asynchronous operation is selected, the 32 kHz Oscillator for Timer/Counter0
is always running, except in Power-down mode. After a Power-up Reset or wake-up
from Power-down, the user should be aware of the fact that this Oscillator might take
as long as one second to stabilize. The user is advised to wait for at least one
second before using Timer/Counter0 after Power-up or wake-up from Power-down.
The content of all Timer/Counter0 Registers must be considered lost after a wake-
up from Power-down due to the unstable clock signal upon start-up, no matter
whether the Oscillator is in use or a clock signal is applied to the TOSC pin.
Description of wake-up from Power-save mode when the Timer is clocked
asynchronously: When the interrupt condition is met, the wake-up process is started
on the following cycle of the Timer clock, that is, the Timer is always advanced by at
least one before the processor can read the counter value. To execute the
corresponding Timer/Counter0 interrupt routine, the Global Interrupt bit in SREG
must have been set. Otherwise, the part will still wake up from Power-down, but
continues to execute the Sleep command. The Interrupt Flags are updated three
processor cycles after the processor clock has started. During these cycles, the
processor executes instructions, but the interrupt condition is not readable and the
interrupt routine has not started yet.
During asynchronous operation, the synchronization of the Interrupt Flags for the
asynchronous Timer takes three processor cycles plus one timer cycle. The Timer is
therefore advanced by at least one before the processor can read the Timer value
causing the setting of the Interrupt Flag. The Output Compare pin is changed on the
Timer clock, and is not synchronized to the processor clock.
After waking up from Power-save mode with the asynchronous Timer enabled, there
will be a short interval of which TCNT0 will read as the same value as before Power-
0945I–AVR–02/07