ATMEGA103-6AC Atmel, ATMEGA103-6AC Datasheet - Page 60

• Manufacturer Part Number: ATMEGA103-6AC
• Description: IC MCU 128K 6MHZ A/D 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA103-6AC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Serial Peripheral
Interface – SPI
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ATmega103(L)
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer
between the ATmega103(L) and peripheral devices or between several AVR devices.
The ATmega103(L) SPI features include the following:
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Figure 37. SPI Block Diagram
The interconnection between Master and Slave CPUs with SPI is shown in Figure 38.
The PB1 (SCK) pin is the clock output in the Master mode and is the clock input in the
Slave mode. Writing to the SPI Data Register of the Master CPU starts the SPI clock
generator, and the data written shifts out of the PB2 (MOSI) pin and into the PB2 (MOSI)
pin of the Slave CPU. After shifting one byte, the SPI clock generator stops, setting the
End-of-Transmission Flag (SPIF). If the SPI interrupt enable bit (SPIE) in the SPCR
Register is set, an interrupt is requested. The Slave Select input, PB0(SS), is set low to
select an individual Slave SPI device. The two Shift Registers in the Master and the
Slave can be considered as one distributed 16-bit circular Shift Register. This is shown
in Figure 38. When data is shifted from the Master to the Slave, data is also shifted in
the opposite direction, simultaneously. This means that during one shift cycle, data in
the Master and the Slave are interchanged.
Full-duplex, Three-wire Synchronous Data Transfer
Master or Slave Operation
LSB First or MSB First Data Transfer
Four Programmable Bit Rates
End-of-Transmission Interrupt Flag
Write Collision Flag Protection
Wake-up from Idle Mode (Slave Mode only)
0945I–AVR–02/07