ATMEGA103-6AI Atmel, ATMEGA103-6AI Datasheet - Page 43

IC MCU 128K 6MHZ A/D IT 64TQFP

ATMEGA103-6AI

Manufacturer Part Number
ATMEGA103-6AI
Description
IC MCU 128K 6MHZ A/D IT 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA103-6AI

Core Processor
AVR
Core Size
8-Bit
Speed
6MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Timer/Counter0 Output
Compare Register – OCR0
Timer/Counter2 Output
Compare Register – OCR2
Timer/Counters 0 and 2 in
PWM Mode
0945I–AVR–02/07
These 8-bit registers contain the value of the Timer/Counters.
Both Timer/Counters are realized as up or up/down (in PWM mode) counters with read
and write access. If the Timer/Counter is written to and a clock source is selected, it con-
tinues counting in the timer clock cycle after it is preset with the written value.
The Output Compare Registers are 8-bit read/write registers.
The Timer/Counter Output Compare Registers contain the data to be continuously com-
pared with the Timer/Counter. Actions on compare matches are specified in TCCR0 and
TCCR2. A compare match does only occur if the Timer/Counter counts to the OCR
value. A software write that sets the Timer/Counter and Output Compare Register to the
same value does not generate a compare match.
A compare match will set the Compare Interrupt Flag in the CPU clock cycle following
the compare event.
When the PWM mode is selected, the Timer/Counter and the Output Compare Register
(OCR0 or OCR2) form an 8-bit, free-running, glitch-free and phase correct PWM with
outputs on the PB4(OC0/PWM0) or PB7(OC2/PWM2) pin. The Timer/Counter acts as
an up/down counter, counting up from $00 to $FF, where it turns and counts down again
to zero before the cycle is repeated. When the counter value matches the contents of
the Output Compare Register, the PB4(OC0/PWM0) or PB7(OC2/PWM2) pin is set or
cleared according to the settings of the COM01/COM00 or COM21/COM20 bits in the
Timer/Counter Control Registers TCCR0 and TCCR2. Refer to Table 13 for details.
Table 13. Compare Mode Select in PWM Mode
Note:
Note that in PWM mode, the Output Compare Register is transferred to a temporary
location when written. The value is latched when the Timer/Counter reaches $FF. This
prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsyn-
chronized OCR0 or OCR2 write. See Figure 32 for an example.
Bit
$31 ($51)
Read/Write
Initial Value
Bit
$23 ($43)
Read/Write
Initial Value
COMn1
0
0
1
1
n = 0 or 2
COMn0
MSB
MSB
0
1
0
1
R/W
R/W
7
0
7
0
Effect on Compare/PWM Pin
Not connected
Not connected
Cleared on compare match, up-counting. Set on compare match, down-
counting (non-inverted PWM).
Cleared on compare match, down-counting. Set on compare match, up-
counting (inverted PWM).
R/W
R/W
6
0
6
0
R/W
R/W
5
0
5
0
R/W
R/W
4
0
4
0
R/W
R/W
3
0
3
0
R/W
R/W
2
0
2
0
ATmega103(L)
R/W
R/W
1
0
1
0
LSB
R/W
LSB
R/W
0
0
0
0
OCR0
OCR2
43

Related parts for ATMEGA103-6AI