ATMEGA103-6AI Atmel, ATMEGA103-6AI Datasheet - Page 53
Manufacturer Part Number
IC MCU 128K 6MHZ A/D IT 64TQFP
Specifications of ATMEGA103-6AI
POR, PWM, WDT
Number Of I /o
Program Memory Size
128KB (64K x 16)
Program Memory Type
4K x 8
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
-40°C ~ 85°C
Package / Case
For Use With
ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Timer/Counter1 in PWM Mode
The Input Capture Register is a 16-bit read-only register.
When the rising or falling edge (according to the Input Capture edge setting (ICES1)) of
the signal at the Input Capture pin – PD4(IC1) – is detected, the current value of the
Timer/Counter1 is transferred to the Input Capture Register (ICR1). At the same time,
the Input Capture Flag (ICF1) is set (one).
Since the Input Capture Register (ICR1) is a 16-bit register, a temporary register TEMP
is used when ICR1 is read to ensure that both bytes are read simultaneously. When the
CPU reads the Low Byte ICR1L, the data is sent to the CPU and the data of the High
Byte ICR1H is placed in the TEMP Register. When the CPU reads the data in the High
Byte ICR1H, the CPU receives the data in the TEMP Register. Consequently, the Low
Byte ICR1L must be accessed first for a full 16-bit register read operation.
The TEMP Register is also used when accessing TCNT1, OCR1A and OCR1B. If the
main program and interrupt routines perform access to registers using TEMP, interrupts
must be disabled during access from the main program.
When the PWM mode is selected, Timer/Counter1, the Output Compare Register1A
(OCR1A) and the Output Compare Register1B (OCR1B) form a dual 8-, 9- or 10-bit,
free-running, glitch-free and phase-correct PWM with outputs on the PB5(OC1A) and
PB6(OC1B) pins. Timer/Counter1 acts as an up/down counter, counting up from $0000
to TOP (see Table 16), where it turns and counts down again to zero before the cycle is
repeated. When the counter value matches the contents of the 10 least significant bits of
OCR1A or OCR1B, the PB5(OC1A)/PB6(OC1B) pins are set or cleared according to the
settings of the COM1A1/COM1A0 or COM1B1/COM1B0 bits in the Timer/Counter1
Control Register, TCCR1A. Refer to Table 19 for details.
Table 18. Timer TOP Values and PWM Frequency
Table 19. Compare1 Mode Select in PWM Mode
Note that in the PWM mode, the 10 least significant OCR1A/OCR1B bits, when written,
are transferred to a temporary location. They are latched when Timer/Counter1 reaches
X = A or B
Effect on OCX1
Cleared on compare match, up-counting. Set on compare match,
down-counting (non-inverted PWM).
Cleared on compare match, down-counting. Set on compare match,
up-counting (inverted PWM).
Timer TOP value