ATMEGA103-6AI Atmel, ATMEGA103-6AI Datasheet - Page 69

IC MCU 128K 6MHZ A/D IT 64TQFP

ATMEGA103-6AI

Manufacturer Part Number
ATMEGA103-6AI
Description
IC MCU 128K 6MHZ A/D IT 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA103-6AI

Core Processor
AVR
Core Size
8-Bit
Speed
6MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Bonase Electronics (HK) Co., Limited Bonase Electronics (HK) Co., Limited
Part Number:
ATMEGA103-6AI
Manufacturer:
ATMEL
Quantity:
586
Price:
ATmega103(L)
Figure 43. Sampling Received Data
RXD
START BIT
D0
D1
D2
D3
D4
D5
D6
D7
STOP BIT
RECEIVER
SAMPLING
When the stop bit enters the Receiver, the majority of the three samples must be one to
accept the stop bit. If two or more samples are logical “0”s, the Framing Error (FE) Flag
in the UART Status Register (USR) is set when the received byte is transferred to UDR.
Before reading the UDR Register, the user should always check the FE bit to detect
Framing Errors. FE is cleared when UDR is read.
Whether or not a valid stop bit is detected at the end of a character reception cycle, the
data is transferred to UDR and the RXC Flag in USR is set. UDR is in fact two physically
separate registers, one for transmitted data and one for received data. When UDR is
read, the Receive Data Register is accessed, and when UDR is written, the Transmit
Data Register is accessed. If 9-bit data word is selected (the CHR9 bit in the UART Con-
trol Register, UCR is set), the RXB8 bit in UCR is loaded with bit 9 in the Transmit Shift
Register when data is transferred to UDR.
If, after having received a character, the UDR Register has not been accessed since the
last receive, the OverRun (OR) flag in USR is set. This means that the new data trans-
ferred to the Shift Register could not be transferred to UDR and is lost. The OR bit is
buffered, and is available when the valid data byte in UDR has been read. The user
should always check the OR after reading from the UDR Register in order to detect any
OverRuns if the baud rate is high or CPU load is high.
When the RXEN bit in the UCR Register is cleared (zero), the Receiver is disabled. This
means that the PE0 pin can be used as a general I/O pin. When RXEN is set, the UART
Receiver will be connected to PE0, which is forced to be an input pin regardless of the
setting of the DDE0 bit in DDRE. When PE0 is forced to input by the UART, the
PORTE0 bit can still be used to control the pull-up resistor on the pin.
When the CHR9 bit in the UCR Register is set, transmitted and received characters are
9 bits long plus start and stop bits. The 9th data bit to be transmitted is the TXB8 bit in
UCR Register. This bit must be set to the wanted value before a transmission is initated
by writing to the UDR Register.
69
0945I–AVR–02/07

Related parts for ATMEGA103-6AI