ATMEGA103-6AI Atmel, ATMEGA103-6AI Datasheet - Page 8

IC MCU 128K 6MHZ A/D IT 64TQFP

ATMEGA103-6AI

Manufacturer Part Number
ATMEGA103-6AI
Description
IC MCU 128K 6MHZ A/D IT 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA103-6AI

Core Processor
AVR
Core Size
8-Bit
Speed
6MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Bonase Electronics (HK) Co., Limited Bonase Electronics (HK) Co., Limited
Part Number:
ATMEGA103-6AI
Manufacturer:
ATMEL
Quantity:
586
Price:
Architectural
Overview
8
ATmega103(L)
Figure 4. The ATmega103(L) AVR RISC Architecture
The AVR uses a Harvard architecture concept – with separate memories and buses for
program and data. The Program memory is accessed with a single-level pipeline. While
one instruction is being executed, the next instruction is pre-fetched from the Program
memory. This concept enables instructions to be executed in every clock cycle. The
Program memory is In-System Programmable Flash memory. With a few exceptions,
AVR instructions have a single 16-bit word format, meaning that every Program memory
address contains a single 16-bit instruction.
During interrupts and subroutine calls, the return address Program Counter (PC) is
stored on the Stack. The Stack is effectively allocated in the general data SRAM and,
consequently, the Stack size is only limited by the total SRAM size and the usage of the
SRAM. All user programs must initialize the SP in the reset routine (before subroutines
or interrupts are executed). The 16-bit Stack Pointer (SP) is read/write accessible in the
I/O space.
The 4000 bytes data SRAM can be easily accessed through the five different address-
ing modes supported in the AVR architecture.
A flexible interrupt module has its control registers in the I/O space with an additional
Global Interrupt Enable bit in the Status Register. All the different interrupts have a sep-
Control Lines
Instruction
Instruction
64K x 16
Program
Register
Decoder
Memory
AVR ATmega103(L) Architecture
Program
Counter
Registers
and Test
Purpose
General
Data Bus 8-bit
Status
32 x 8
SRAM
4K x 8
ALU
Data
Peripherals
EEPROM
0945I–AVR–02/07
4K x 8

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