AT91M40800-33AI Atmel, AT91M40800-33AI Datasheet - Page 90
AT91M40800-33AI
Manufacturer Part Number
AT91M40800-33AI
Description
IC ARM7 MCU 100 TQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheets
1.AT91M40800-33AU.pdf
(18 pages)
2.AT91R40807-33AI.pdf
(153 pages)
3.AT91M40800-33AI.pdf
(21 pages)
Specifications of AT91M40800-33AI
Core Processor
ARM7
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, UART/USART
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91M40800-33AI
Manufacturer:
ATMEL
Quantity:
40
Company:
Part Number:
AT91M40800-33AI
Manufacturer:
QFP
Quantity:
319
Part Number:
AT91M40800-33AI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
WD User Interface
WD Base Address: 0xFFFF8000 (Code Label WD_BASE)
Table 12. WD Memory Map
WD Overflow Mode Register
Name:
Access:
Reset Value: 0
Offset:
• WDEN: Watch Dog Enable (Code Label WD_WDEN)
0 = Watch Dog is disabled and does not generate any signals.
1 = Watch Dog is enabled and generates enabled signals.
• RSTEN: Reset Enable (Code Label WD_RSTEN)
0 = Generation of an internal reset by the Watch Dog is disabled.
1 = When overflow occurs, the Watch Dog generates an internal reset.
• IRQEN: Interrupt Enable (Code Label WD_IRQEN)
0 = Generation of an interrupt by the Watch Dog is disabled.
1 = When overflow occurs, the Watch Dog generates an interrupt.
• EXTEN: External Signal Enable (Code Label WD_EXTEN)
0 = Generation of a pulse on the pin NWDOVF by the Watch Dog is disabled.
1 = When an overflow occurs, a pulse on the pin NWDOVF is generated.
• OKEY: Overflow Access Key (Code Label WD_OKEY)
Used only when writing WD_OMR. OKEY is read as 0.
0x234 = Write access in WD_OMR is allowed.
Other value = Write access in WD_OMR is prohibited.
90
31
23
15
Offset
–
–
7
0x0C
0x00
0x04
0x08
AT91X40 Series
WD_OMR
Read/Write
0x00
Register
Overflow Mode Register
Clock Mode Register
Control Register
Status Register
30
22
14
–
–
6
OKEY
29
21
13
–
–
5
28
20
12
–
–
4
OKEY
EXTEN
27
19
11
–
–
3
WD_OMR
WD_CMR
WD_CR
WD_SR
Name
IRQEN
26
18
10
–
–
2
Read/Write
Read/Write
Read Only
Write Only
Access
RSTEN
25
17
–
–
9
1
1354D–ATARM–08/02
Reset State
WDEN
0
0
–
0
24
16
–
–
8
0