ATMEGA163-8AI Atmel, ATMEGA163-8AI Datasheet - Page 65
ATMEGA163-8AI
Manufacturer Part Number
ATMEGA163-8AI
Description
IC AVR MCU 16K A/D 8MHZ 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA163-8AC.pdf
(187 pages)
Specifications of ATMEGA163-8AI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA163-8AI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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Serial Peripheral
Interface – SPI
1142E–AVR–02/03
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer
between the ATmega163 and peripheral devices or between several AVR devices. The
ATmega163 SPI includes the following features:
•
•
•
•
•
•
•
•
Figure 41. SPI Block Diagram
The interconnection between Master and Slave CPUs with SPI is shown in Figure 42.
The PB7(SCK) pin is the clock output in the Master mode and the clock input in the
Slave mode. Writing to the SPI Data Register of the Master CPU starts the SPI clock
generator, and the data written shifts out of the PB5(MOSI) pin and into the PB5(MOSI)
pin of the Slave CPU. After shifting one byte, the SPI Clock Generator stops, setting the
end of Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR
Register is set, an interrupt is requested. The Slave Select input, PB4(SS), is set low to
select an individual Slave SPI device. The two Shift Registers in the Master and the
Slave can be considered as one distributed 16-bit circular Shift Register. This is shown
in Figure 42. When data is shifted from the Master to the Slave, data is also shifted in
Full-duplex, Three-wire Synchronous Data Transfer
Master or Slave Operation
LSB First or MSB First Data Transfer
Seven Programmable Bit Rates
End of Transmission Interrupt Flag
Write Collision Flag Protection
Wake-up from Idle Mode
Double Speed (CK/2) Master SPI Mode
/2/4/8/16/32/64/128
DIVIDER
ATmega163(L)
65
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