ATMEGA163L-4PC Atmel, ATMEGA163L-4PC Datasheet - Page 8
ATMEGA163L-4PC
Manufacturer Part Number
ATMEGA163L-4PC
Description
IC AVR MCU 16K A/D 2.7V 40DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA163-8AC.pdf
(187 pages)
Specifications of ATMEGA163L-4PC
Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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8
ATmega163(L)
Figure 5. The ATmega163 AVR RISC Architecture
The AVR uses a Harvard architecture concept – with separate memories and buses for
program and data. The Program memory is executed with a two stage pipeline. While
one instruction is being executed, the next instruction is pre-fetched from the Program
memory. This concept enables instructions to be executed in every clock cycle. The
Program memory is In-System Re-programmable Flash memory.
With the jump and call instructions, the whole 8K word address space is directly
accessed. Most AVR instructions have a single 16-bit word format. Every program
memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section (256
to 2,048 bytes, see page 134) and the Application Program section. Both sections have
dedicated Lock bits for write and read/write protection. The SPM instruction that writes
into the Application Flash memory section is allowed only in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is
stored on the Stack. The Stack is effectively allocated in the general data SRAM, and
consequently the Stack size is only limited by the total SRAM size and the usage of the
SRAM. All user programs must initialize the SP in the reset routine (before subroutines
or interrupts are executed). The 11-bit Stack Pointer SP is read/write accessible in the
I/O space.
Control Lines
Instruction
Instruction
8K X 16
Program
Register
Decoder
Memory
Program
Counter
and Control
Registrers
1024 x 8
EEPROM
512 x 8
I/O Lines
Purpose
General
SRAM
Data Bus 8-bit
Status
32 x 8
Data
ALU
32
A/D Converter
Two-wire Serial
Timer/Counter
Timer/Counter
Timer/Counter
Comparator
with PWM
with PWM
Watchdog
Analog
Interrupt
Interface
1142E–AVR–02/03
16-bit
Timer
UART
Serial
8-bit
8-bit
Unit
Unit
SPI
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