AT89C51-24JC Atmel, AT89C51-24JC Datasheet - Page 5

IC MICRO CTRL 24MHZ 44PLCC

AT89C51-24JC

Manufacturer Part Number
AT89C51-24JC
Description
IC MICRO CTRL 24MHZ 44PLCC
Manufacturer
Atmel
Series
89Cr
Datasheet

Specifications of AT89C51-24JC

Core Processor
8051
Core Size
8-Bit
Speed
24MHz
Connectivity
UART/USART
Number Of I /o
32
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-PLCC
Data Bus Width
8 bit
Data Ram Size
128 B
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
32
Number Of Timers
2
Operating Supply Voltage
0 V to 6.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Peripherals
-
Lead Free Status / Rohs Status
No

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Figure 2. External Clock Drive Configuration
Power-down Mode
In the power-down mode, the oscillator is stopped, and the
instruction that invokes power-down is the last instruction
executed. The on-chip RAM and Special Function Regis-
Lock Bit Protection Modes
1
2
3
4
Program Lock Bits
LB1
U
P
P
P
LB2
U
U
P
P
LB3
U
U
U
P
Protection Type
No program lock features
MOVC instructions executed from external program memory are disabled from
fetching code bytes from internal memory, EA is sampled and latched on reset,
and further programming of the Flash is disabled
Same as mode 2, also verify is disabled
Same as mode 3, also external execution is disabled
ters retain their values until the power-down mode is
terminated. The only exit from power-down is a hardware
reset. Reset redefines the SFRs but does not change the
on-chip RAM. The reset should not be activated before V
is restored to its normal operating level and must be held
active long enough to allow the oscillator to restart and
stabilize.
Program Memory Lock Bits
On the chip are three lock bits which can be left unpro-
grammed (U) or can be programmed (P) to obtain the
additional features listed in the table below.
When lock bit 1 is programmed, the logic level at the EA pin
is sampled and latched during reset. If the device is pow-
ered up without a reset, the latch initializes to a random
value, and holds that value until reset is activated. It is nec-
essary that the latched value of EA be in agreement with
the current logic level at that pin in order for the device to
function properly.
CC
5

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