AT89C5131A-RDTIL Atmel, AT89C5131A-RDTIL Datasheet - Page 124
AT89C5131A-RDTIL
Manufacturer Part Number
AT89C5131A-RDTIL
Description
IC 8051 MCU FLASH 32K USB 64VQFP
Manufacturer
Atmel
Series
AT89C513xr
Specifications of AT89C5131A-RDTIL
Core Processor
C52X2
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
LED, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-05 - KIT STARTER FOR AT89C5131
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
-
Other names
AT89C5131-RDTIL
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Bulk/Interrupt IN Transactions
in Standard Mode
124
AT89C5131A-L
Figure 64. Bulk/Interrupt IN Transactions in Standard Mode
An endpoint will be first enabled and configured before being able to send Bulk or Inter-
rupt packets.
The firmware will fill the FIFO with the data to be sent and set the TXRDY bit in the UEP-
STAX register to allow the USB controller to send the data stored in FIFO at the next IN
request concerning this endpoint. To send a Zero Length Packet, the firmware will set
the TXRDY bit without writing any data into the endpoint FIFO.
Until the TXRDY bit has been set by the firmware, the USB controller will answer a NAK
handshake for each IN requests.
To cancel the sending of this packet, the firmware has to reset the TXRDY bit. The
packet stored in the endpoint FIFO is then cleared and a new packet can be written and
sent.
When the IN packet has been sent and acknowledged by the Host, the TXCMPL bit in
the UEPSTAX register is set by the USB controller. This triggers a USB interrupt if
enabled. The firmware will clear the TXCMPL bit before filling the endpoint FIFO with
new data.
The firmware will never write more bytes than supported by the endpoint FIFO.
All USB retry mechanisms are automatically managed by the USB controller.
IN
HOST
IN
ACK
DATA0 (n Bytes)
NAK
UFI
TXCMPL
Endpoint FIFO Write Byte 1
Endpoint FIFO Write Byte 1
Endpoint FIFO Write Byte 2
Endpoint FIFO Write Byte n
Clear TXCMPL
Set TXRDY
C51
4338F–USB–08/07
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