AT89C5132-ROTIL Atmel, AT89C5132-ROTIL Datasheet - Page 68
![IC 8051 MCU FLASH 64K USB 80TQFP](/photos/12/13/121358/313-80-tqfp_sml.jpg)
AT89C5132-ROTIL
Manufacturer Part Number
AT89C5132-ROTIL
Description
IC 8051 MCU FLASH 64K USB 80TQFP
Manufacturer
Atmel
Series
AT89C513xr
Datasheets
1.AT89C5132-ROTUL.pdf
(182 pages)
2.AT89C5132-ROTUL.pdf
(38 pages)
3.AT89C5132-ROTIL.pdf
(33 pages)
Specifications of AT89C5132-ROTIL
Core Processor
C52X2
Core Size
8-Bit
Speed
20MHz
Connectivity
IDE/ATAPI, I²C, MMC, PCM, SPI, UART/USART, USB
Peripherals
I²S, POR, WDT
Number Of I /o
44
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 2x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Manufacturer
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15.1
15.1.1
68
Description
AT89C5132
Clock Controller
The USB device controller provides the hardware that the AT89C5132 need to interface a USB
link to data flow stored in a double port memory.
It requires a 48 MHz reference clock provided by the clock controller as detailed in Section
"Clock Controller", page 68. This clock is used to generate a 12 MHz Full Speed bit clock from
the received USB differential data flow and to transmit data according to full speed USB device
tolerance. Clock recovery is done by a Digital Phase Locked Loop (DPLL) block.
The Serial Interface Engine (SIE) block performs NRZI encoding and decoding, bit stuffing, CRC
generation and checking, and the serial-parallel data conversion.
The Universal Function Interface (UFI) controls the interface between the data flow and the Dual
Port RAM, but also the interface with the C51 core itself.
Figure 15-3 shows how to connect the AT89C5132 to the USB connector. D+ and D- pins are
connected through 2 termination resistors. A pull-up resistor is implemented on D+ to inform the
host of a full speed device connection. Value of these resistors is detailed in the section “DC
Characteristics”.
Figure 15-1. USB Device Controller Block Diagram
Figure 15-2. USB Connection
The USB controller clock is generated by division of the PLL clock. The division factor is given by
USBCD1:0 Bits in USBCLK register (see Table 70). Figure 15-3 shows the USB controller clock
CLOCK
USB
D+
D-
48 MHz
Buffer
USB
VBUS
GND
D+
D-
DPLL
VSS
To Power
Supply
SIE
VDD
12 MHz
R
FS
R
R
USB
USB
D+
D-
UFI
4173E–USB–09/07
To/From
C51 Core
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