ATMEGA48-20AI Atmel, ATMEGA48-20AI Datasheet - Page 298

• Manufacturer Part Number: ATMEGA48-20AI
• Description: IC AVR MCU 4K 5V 20MHZ 32-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA48-20AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFP, 32-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA48-24AI; ATMEGA48-24AI

27.8.1
27.8.2
298
ATmega48/88/168
Serial Programming Pin Mapping
Serial Programming Algorithm
Table 27-15. Pin Mapping Serial Programming
When writing serial data to the ATmega48/88/168, data is clocked on the rising edge of SCK.
When reading data from the ATmega48/88/168, data is clocked on the falling edge of SCK. See
Figure 27-9
To program and verify the ATmega48/88/168 in the serial programming mode, the following
sequence is recommended (See Serial Programming Instruction set in
299):
1. Power-up sequence:
2. Wait for at least 20 ms and enable serial programming by sending the Programming
3. The serial programming instructions will not work if the communication is out of synchro-
4. The Flash is programmed one page at a time. The memory page is loaded one byte at a
5. A: The EEPROM array is programmed one byte at a time by supplying the address and
Apply power between V
tems, the programmer can not guarantee that SCK is held low during power-up. In this
case, RESET must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
Enable serial instruction to pin MOSI.
nization. When in sync. the second byte (0x53), will echo back when issuing the third
byte of the Programming Enable instruction. Whether the echo is correct or not, all four
bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a
positive pulse and issue a new Programming Enable command.
time by supplying the 6 LSB of the address and data together with the Load Program
Memory Page instruction. To ensure correct loading of the page, the data low byte must
be loaded before data high byte is applied for a given address. The Program Memory
Page is stored by loading the Write Program Memory Page instruction with the 7 MSB of
the address. If polling (RDY/BSY) is not used, the user must wait at least t
issuing the next page (See
before the Flash write operation completes can result in incorrect programming.
data together with the appropriate Write instruction. An EEPROM memory location is first
automatically erased before new data is written. If polling (RDY/BSY) is not used, the
user must wait at least t
chip erased device, no 0xFFs in the data file(s) need to be programmed.
B: The EEPROM array is programmed one page at a time. The Memory page is loaded
one byte at a time by supplying the 6 LSB of the address and data together with the Load
EEPROM Memory Page instruction. The EEPROM Memory Page is stored by loading
the Write EEPROM Memory Page Instruction with the 7 MSB of the address. When using
EEPROM page access only byte locations loaded with the Load EEPROM Memory Page
instruction is altered. The remaining locations remain unchanged. If polling (RDY/BSY) is
not used, the used must wait at least t
27-16). In a chip erased device, no 0xFF in the data file(s) need to be programmed.
Symbol
MOSI
MISO
SCK
for timing details.
CC
WD_EEPROM
Pins
PB3
PB4
PB5
and GND while RESET and SCK are set to “0”. In some sys-
Table
27-16). Accessing the serial programming interface
before issuing the next byte (See
WD_EEPROM
I/O
O
I
I
before issuing the next byte (See
Serial Data out
Serial Data in
Description
Table 27-17 on page
Serial Clock
Table
WD_FLASH
27-16). In a
2545S–AVR–07/10
before
Table