ATMEGA88-20AJ Atmel, ATMEGA88-20AJ Datasheet - Page 162

IC MCU AVR 8K 5V 20MHZ 32-TQFP

ATMEGA88-20AJ

Manufacturer Part Number
ATMEGA88-20AJ
Description
IC MCU AVR 8K 5V 20MHZ 32-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA88-20AJ

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATMEGA88-24AJ
ATMEGA88-24AJ

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Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA88-20AJ
Manufacturer:
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Quantity:
10 000
162
ATmega48/88/168
Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an interrupt
is requested. The Slave may continue to place new data to be sent into SPDR before reading
the incoming data. The last incoming byte will be kept in the Buffer Register for later use.
Figure 18-2. SPI Master-slave Interconnection
The system is single buffered in the transmit direction and double buffered in the receive direc-
tion. This means that bytes to be transmitted cannot be written to the SPI Data Register before
the entire shift cycle is completed. When receiving data, however, a received character must be
read from the SPI Data Register before the next character has been completely shifted in. Oth-
erwise, the first byte is lost.
In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure
correct sampling of the clock signal, the minimum low and high periods should be:
Low periods: Longer than 2 CPU clock cycles.
High periods: Longer than 2 CPU clock cycles.
When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden
according to
“Alternate Port Functions” on page
Table 18-1.
Note:
The following code examples show how to initialize the SPI as a Master and how to perform a
simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction
Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the
actual data direction bits for these pins. For example if MOSI is placed on pin PB3, replace
DD_MOSI with DDB3 and DDR_SPI with DDRB.
MOSI
MISO
SCK
Pin
SS
See
direction of the user defined SPI pins.
“Alternate Functions of Port B” on page 77
Table 18-1 on page
SPI Pin Overrides
Direction, Master SPI
User Defined
Input
User Defined
User Defined
(Note:)
162. For more details on automatic port overrides, refer to
75.
for a detailed description of how to define the
Direction, Slave SPI
Input
User Defined
Input
Input
SHIFT
ENABLE
2545S–AVR–07/10

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