ATMEGA88-20MJ Atmel, ATMEGA88-20MJ Datasheet - Page 40

• Manufacturer Part Number: ATMEGA88-20MJ
• Description: IC MCU AVR 8K 5V 20MHZ 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA88-20MJ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATMEGA88-24MJ; ATMEGA88-24MJ

9.6
9.7
9.8
9.8.1
9.8.2
40
Standby Mode
Power Reduction Register
Minimizing Power Consumption
ATmega48/88/168
Analog to Digital Converter
Analog Comparator
If Timer/Counter2 is not running, Power-down mode is recommended instead of Power-save
mode.
The Timer/Counter2 can be clocked both synchronously and asynchronously in Power-save
mode. If Timer/Counter2 is not using the asynchronous clock, the Timer/Counter Oscillator is
stopped during sleep. If Timer/Counter2 is not using the synchronous clock, the clock source is
stopped during sleep. Note that even if the synchronous clock is running in Power-save, this
clock is only available for Timer/Counter2.
When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the
SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down
with the exception that the Oscillator is kept running. From Standby mode, the device wakes up
in six clock cycles.
The Power Reduction Register (PRR), see
vides a method to stop the clock to individual peripherals to reduce power consumption. The
current state of the peripheral is frozen and the I/O registers can not be read or written.
Resources used by the peripheral when stopping the clock will remain occupied, hence the
peripheral should in most cases be disabled before stopping the clock. Waking up a module,
which is done by clearing the bit in PRR, puts the module in the same state as before shutdown.
Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall
power consumption. See
sleep modes, the clock is already stopped.
There are several possibilities to consider when trying to minimize the power consumption in an
AVR controlled system. In general, sleep modes should be used as much as possible, and the
sleep mode should be selected so that as few as possible of the device’s functions are operat-
ing. All functions not needed should be disabled. In particular, the following modules may need
special consideration when trying to achieve the lowest possible power consumption.
If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be dis-
abled before entering any sleep mode. When the ADC is turned off and on again, the next
conversion will be an extended conversion. Refer to
for details on ADC operation.
When entering Idle mode, the Analog Comparator should be disabled if not used. When entering
ADC Noise Reduction mode, the Analog Comparator should be disabled. In other sleep modes,
the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up
to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all
sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep
mode. Refer to
Comparator.
“Analog Comparator” on page 240
“Power-Down Supply Current” on page 322
“PRR – Power Reduction Register” on page
for details on how to configure the Analog
“Analog-to-Digital Converter” on page 243
for examples. In all other
2545S–AVR–07/10
43, pro-