ATMEGA169-16MI SL709 Atmel, ATMEGA169-16MI SL709 Datasheet
ATMEGA169-16MI SL709
Specifications of ATMEGA169-16MI SL709
Related parts for ATMEGA169-16MI SL709
ATMEGA169-16MI SL709 Summary of contents
Page 1
... I/O and Packages – 53 Programmable I/O Lines – 64-lead TQFP and 64-pad QFN/MLF • Speed Grade: – ATmega169V MHz @ 1.8 - 5.5V MHz @ 2.7 - 5.5V – ATmega169 MHz @ 2.7 - 5.5V MHz @ 4.5 - 5.5V • Temperature range: – -40°C to 85°C Industrial • ...
Page 2
... Pin Configurations Disclaimer ATmega169/V 2 Figure 1. Pinout ATmega169 LCDCAP 1 (RXD/PCINT0) PE0 2 INDEX CORNER (TXD/PCINT1) PE1 3 (XCK/AIN0/PCINT2) PE2 4 (AIN1/PCINT3) PE3 5 (USCK/SCL/PCINT4) PE4 6 (DI/SDA/PCINT5) PE5 7 (DO/PCINT6) PE6 8 (CLKO/PCINT7) PE7 9 (SS/PCINT8) PB0 10 (SCK/PCINT9) PB1 11 (MOSI/PCINT10) PB2 12 (MISO/PCINT11) PB3 13 (OC0A/PCINT12) PB4 14 (OC1A/PCINT13) PB5 15 (OC1B/PCINT14) PB6 16 Note: The large center pad underneath the QFN/MLF packages is made of metal and internally connected to GND ...
Page 3
... Overview The ATmega169 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega169 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram Figure 2 ...
Page 4
... In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega169 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega169 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Cir- cuit Emulators, and Evaluation kits. ...
Page 5
... The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the ATmega169 as listed on page 66. Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit) ...
Page 6
... The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port G also serves the functions of various special features of the ATmega169 as listed on page 70. Reset input. A low level on this pin for longer than the minimum pulse length will gener- ate a reset, even if the clock is not running ...
Page 7
... USART I/O Data Register USART Baud Rate Register Low – – – UMSEL UPM1 UPM0 USBS TXCIE UDRIE RXEN TXEN TXC UDRE FE DOR ATmega169/V Bit 2 Bit 1 Bit 0 – – – – – – – SEG324 SEG318 SEG317 SEG316 SEG310 SEG309 SEG308 ...
Page 8
... TCNT1H (0x84) TCNT1L (0x83) Reserved – (0x82) TCCR1C FOC1A (0x81) TCCR1B ICNC1 (0x80) TCCR1A COM1A1 (0x7F) DIDR1 – (0x7E) DIDR0 ADC7D ATmega169/V 8 Bit 6 Bit 5 Bit 4 Bit 3 – – – – – – – – – – – – – – – ...
Page 9
... EEPROM Address Register Low Byte EEPROM Data Register – – – EERIE General Purpose I/O Register 0 PCIE0 – – PCIF0 – – ATmega169/V Bit 2 Bit 1 Bit 0 – – – – MUX2 MUX1 MUX0 – ADTS2 ADTS1 ADTS0 ADPS2 ...
Page 10
... When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega169 is a com- plex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions ...
Page 11
... PC ← then PC ← then PC ← then PC ← then PC ← ⊕ then PC ← ⊕ then PC ← then PC ← then PC ← then PC ← then PC ← then PC ← then PC ← ATmega169/V Operation Flags #Clocks Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V ...
Page 12
... Store Program Memory IN Rd Port OUT P, Rr Out Port PUSH Rr Push Register on Stack ATmega169/V 12 Description then PC ← then PC ← I/O(P,b) ← 1 I/O(P,b) ← 0 Rd(n+1) ← Rd(n), Rd(0) ← 0 Rd(n) ← Rd(n+1), Rd(7) ← 0 Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Rd(n) ← ...
Page 13
... MCU CONTROL INSTRUCTIONS NOP No Operation SLEEP Sleep WDR Watchdog Reset BREAK Break 2514PS–AVR–07/06 Description Rd ← STACK (see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-chip Debug Only ATmega169/V Operation Flags #Clocks None None None None None N/A 13 ...
Page 14
... Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) ATmega169/V 14 Ordering Code Package ATmega169V-8AI 64A (2) ATmega169V-8AU 64A ATmega169V-8MI 64M1 (2) ATmega169V-8MU 64M1 ATmega169-16AI 64A (2) ATmega169-16AU 64A ATmega169-16MI 64M1 (2) ATmega169-16MU 64M1 Package Type (1) Operation Range Industrial 0°C to 85°C) (-4 Industrial 0°C to 85°C) (-4 2514PS–AVR–07/06 ...
Page 15
... Orchard Parkway San Jose, CA 95131 R 2514PS–AVR–07/06 B PIN 1 IDENTIFIER TITLE 64A, 64-lead Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) ATmega169/V A COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX SYMBOL NOM NOTE A – – 1.20 A1 0.05 – ...
Page 16
... D Marked Pin TOP VIEW BOTTOM VIEW Note: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD. 2. Dimension and tolerance conform to ASMEY14.5M-1994. 2325 Orchard Parkway San Jose, CA 95131 R ATmega169 Pin #1 Corner Pin #1 1 Option A Triangle 2 3 Option B Pin #1 Chamfer (C 0.30) Option C Pin #1 Notch e (0 ...
Page 17
... The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are replaced by all-ones during Update-DR. Problem Fix / Workaround – If ATmega169 is the only device in the scan chain, the problem is not visible. – Select the Device ID Register of the ATmega169 by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain ...
Page 18
... ATmega169 Rev C ATmega169/V 18 • Interrupts may be lost when writing the timer registers in the asynchronous timer • High Current Consumption In Power Down when JTAGEN is Programmed • LCD Contrast Control • Some Data Combinations Can Result in Dim Segments on the LCD • LCD Current Consumption • ...
Page 19
... ATmega169 Rev B 2514PS–AVR–07/06 Problem Fix / Workaround – If ATmega169 is the only device in the scan chain, the problem is not visible. – Select the Device ID Register of the ATmega169 by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain ...
Page 20
... The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are replaced by all-ones during Update-DR. Problem Fix / Workaround – If ATmega169 is the only device in the scan chain, the problem is not visible. – Select the Device ID Register of the ATmega169 by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain ...
Page 21
... Updated “Serial Peripheral Interface – SPI” on page 143. 1. Added Not recommended in new designs. 2. Removed the notice: This datasheet covers revision ATmega169. Revision F and onwards are now covered in ATmega169 datasheet, “doc2597.pdf” found on www.atmel.com/avr. 3. Updated Table 17 on page 40. 1. This datasheet covers revision ATmega169. ...
Page 22
... Removed old and added new “LCD Controller” on page 209. 7. Updated “Electrical Characteristics” on page 297. 8. Updated “ATmega169 Typical Characteristics” on page 304. 9. Updated “Ordering Information” on page 14. ATmega169L replaced by ATmega169V and ATmega169. 1. Updated “Calibrated Internal RC Oscillator” on page 27 1. Removed “ ...
Page 23
... Rev. 2514E-02/03 2514PS–AVR–07/06 1. Updated typo in Figure 148, Figure 168, and Figure 195. 1. Updated “ATmega169 Typical Characteristics” on page 304. 2. Updated typo in “Ordering Information” on page 14. 3. Updated Figure 46 on page 109, Table 18 on page 40, and “Version” on page 232. ...
Page 24
... ATmega169 Updated the “Ordering Information” on page 14 to include the new speed grade for ATmega169L and the new 16 MHz ATmega169. 1. Added TCK frequency limit in “Programming via the JTAG Interface” on page 284. 2. Added Chip Erase as a first step in “Programming the Flash” on page 294 and “ ...
Page 25
... Added “Errata” on page 17. 2. Added Information for the 64-pad MLF Package in “Ordering Information” on page 14 and “Packaging Information” on page 15. 3. Changed Temperature Range and Removed Industrial Ordering Codes in “Packaging Information” on page 15. 1. Changed the Endurance on the Flash to 10,000 Write/Erase Cycles. ATmega169/V 25 ...
Page 26
... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...