AT91SAM7A1-AU Atmel, AT91SAM7A1-AU Datasheet - Page 102

• Manufacturer Part Number: AT91SAM7A1-AU
• Description: IC ARM7 MCU 32BIT ROMLESS144LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A1-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: AT91SAM7A1-EK - BOARD EVAL FOR AT91SAM7A1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

15.4
Table 15-1.
102
Peripheral
USART0
USART1
USART2
SPI
Capture CAPT0
Capture CAPT1
ADC (8-channel 10-bit)
PDC Configuration
AT91SAM7A1
PDC Connection
The number of transfers required is programmed in the PDC_TCRx which is memory mapped
as a 16-bit read/write register. The number of transfers remaining can be read in the
PDC_TCRx register.
If the PDC_TCRx is re-programmed while the PDC is operating, the number of transfers will
be changed. The PDC will continue to count transfers when triggered, from the newly pro-
grammed value.
The end of transfer is signaled to the peripheral via the PDC_END signal. The PDC does not
have any dedicated status registers.
While the PDC is operating, in order to stop PDC transfers correctly and to get a fixed value in
the PDC_MPRx register, user should write two consecutive '0' values in the PDC_TCRx regis-
ter. In case the second write is not done and if a PDC transfer has started before the first write
in the PDC_TCRx register then PDC_MPRx register value will change during the next core
clock periods.
For emulation purposes, each PDC channel can be software configured to be attached to a
different peripheral.
In the AT91SAM7A1 microcontroller, each PDC channel is attached to a dedicated peripheral
(with a fixed direction and fixed address). Software must configure each PDC channel so the
accesses are correctly done by the PDC module:
The end of transmission or reception for each PDC channel transfer is indicated in the status
register of the attached peripheral. The PDC_TCRx is decremented with the peripheral trigger
Channel
RX: Ch0
RX: Ch2
RX: Ch4
RX: Ch6
TX: Ch1
TX: Ch3
TX: Ch5
TX: Ch7
Ch10
PDC
Ch8
Ch9
Transmission
Transmission
Transmission
Transmission
Reception
Reception
Reception
Reception
Reception
Reception
Reception
Direction
Transfer
PDC_CRx
DIR Bit in
0
1
0
1
0
1
0
1
0
0
0
USART0_RHR
USART1_RHR
USART2_RHR
USART0_THR
USART1_THR
USART2_THR
Associated
CAPT0_DR
CAPT1_DR
Peripheral
SPI_RDR
SPI_TDR
ADC_DR
Register
6048B–ATARM–29-Jun-06
0xFFFDC080
0xFFFAC080
0xFFFAC084
0xFFFB0080
0xFFFB0084
0xFFFB4080
0xFFFB4084
0xFFFE0080
0xFFFC0080
0xFFFA8080
0xFFFA8084
Associated
Peripheral
Address