AT91SAM7A1-AU Atmel, AT91SAM7A1-AU Datasheet - Page 273

• Manufacturer Part Number: AT91SAM7A1-AU
• Description: IC ARM7 MCU 32BIT ROMLESS144LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A1-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: AT91SAM7A1-EK - BOARD EVAL FOR AT91SAM7A1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

25.2.11
25.2.12
25.2.13
25.2.14
25.2.15
25.2.16
25.3
6048B–ATARM–29-Jun-06
Channel Overview
Error Signaling and Recovery Time
Fault Confinement
Connections
Single Channel
Bus Values
Acknowledgement
Total residual error probability for undetected corrupted messages is less than
Corrupted messages are flagged by any node detecting an error. Such messages are aborted
and will be retransmitted automatically. The recovery time from detecting an error until the
start of the next message is at most 31 bit times if there is no further error.
CAN nodes are able to distinguish short disturbances from permanent failures. Defective
nodes are switched off.
The CAN serial communication link is a bus to which a number of units may be connected.
This number has no theoretical limit. In practice, the total number of units is limited by delay
times and/or electrical loads on the bus line.
The bus consists of a single bidirectional channel that carries bits. From this data, resynchroni-
zation information can be derived. The way in which this channel is implemented is not fixed in
this document, e.g., single wire (plus ground), two differential wires, optical fibers, etc.
The bus can have one of two complementary logical values: dominant or recessive. During
simultaneous transmission of dominant and recessive bits, the resulting bus value will be dom-
inant. For example, in case of a wired-AND implementation of the bus, the dominant level is
represented by a logical 0 and the recessive level by a logical 1. Physical states (e.g., electri-
cal voltage, light) that represent the logical levels are not given in this document.
All receivers check the consistency of the message being received and acknowledge a consis-
tent message and flag an inconsistent message.
The CAN module has a set of buffers, also called channels or mailboxes. Each mailbox is
assigned an identifier and can be set to transmit or receive.
It is possible to reconfigure mailboxes dynamically.
When the CAN module receives a message, it checks the mailboxes in order to see if there is
a receive mailbox with the same identifier as the message. If such a mailbox is found, the
message is stored in it. If several mailboxes are configured with the same identifier, only the
smaller channel store the message. If no mailbox is found, the message is discarded.
When the CAN module has to transmit a message, the message length, data and identifier are
written to a mailbox set in transmission. If several messages in different mailboxes are waiting
• All local errors at transmitters are detected by means of monitoring.
• Up to 5 randomly distributed errors in a message are detected by means of CRC.
• Burst errors of length less than 15 in a message are detected by means of CRC.
• Errors of any odd number in a message are detected by means of CRC.
Message Error Rate
4.7
10
11
AT91SAM7A1
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