AT91SAM7S256-AU-001 Atmel, AT91SAM7S256-AU-001 Datasheet

IC ARM7 MCU 32BIT 256K 64LQFP

AT91SAM7S256-AU-001

Manufacturer Part Number
AT91SAM7S256-AU-001
Description
IC ARM7 MCU 32BIT 256K 64LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet

Specifications of AT91SAM7S256-AU-001

Package / Case
64-LQFP
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
55MHz
Number Of I /o
32
Core Processor
ARM7
Program Memory Type
FLASH
Ram Size
64K x 8
Program Memory Size
256KB (256K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, SPI, SSC, UART/USART, USB
Core Size
16/32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
AT91SAM7S256AU001

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Bonase Electronics (HK) Co., Limited Bonase Electronics (HK) Co., Limited
Part Number:
AT91SAM7S256-AU-001
Manufacturer:
EPCOS
Quantity:
4 000
Price:
Features
Incorporates the ARM7TDMI
Internal High-speed Flash
Internal High-speed SRAM, Single-cycle Access at Maximum Speed
Memory Controller (MC)
Reset Controller (RSTC)
Clock Generator (CKGR)
Power Management Controller (PMC)
Advanced Interrupt Controller (AIC)
Debug Unit (DBGU)
Periodic Interval Timer (PIT)
Windowed Watchdog (WDT)
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– EmbeddedICE
– 512 Kbytes (AT91SAM7S512) Organized in Two Contiguous Banks of 1024 Pages
– 256 Kbytes (AT91SAM7S256) Organized in 1024 Pages of 256 Bytes (Single Plane)
– 128 Kbytes (AT91SAM7S128) Organized in 512 Pages of 256 Bytes (Single Plane)
– 64 Kbytes (AT91SAM7S64) Organized in 512 Pages of 128 Bytes (Single Plane)
– 32 Kbytes (AT91SAM7S321/32) Organized in 256 Pages of 128 Bytes (Single Plane)
– 16Kbytes (AT91SAM7S161/16 Organized in 256 Pages of 64 Bytes (Single Plane)
– Single Cycle Access at Up to 30 MHz in Worst Case Conditions
– Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed
– Page Programming Time: 6 ms, Including Page Auto-erase, Full Erase Time: 15 ms
– 10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities,
– Fast Flash Programming Interface for High Volume Production
– 64 Kbytes (AT91SAM7S512/256)
– 32 Kbytes (AT91SAM7S128)
– 16 Kbytes (AT91SAM7S64)
– 8 Kbytes (AT91SAM7S321/32)
– 4 Kbytes (AT91SAM7S161/16)
– Embedded Flash Controller, Abort Status and Misalignment Detection
– Based on Power-on Reset and Low-power Factory-calibrated Brown-out Detector
– Provides External Reset Signal Shaping and Reset Source Status
– Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL
– Software Power Optimization Capabilities, Including Slow Clock Mode (Down to
– Three Programmable External Clock Signals
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Two (AT91SAM7S512/256/128/64/321/161) or One (AT91SAM7S32/16) External
– 2-wire UART and Support for Debug Communication Channel interrupt,
– 20-bit Programmable Counter plus 12-bit Interval Counter
– 12-bit key-protected Programmable Counter
– Provides Reset or Interrupt Signals to the System
– Counter May Be Stopped While the Processor is in Debug State or in Idle Mode
of 256 Bytes (Dual Plane)
Flash Security Bit
500 Hz) and Idle Mode
Interrupt Source(s) and One Fast Interrupt Source, Spurious Interrupt Protected
Programmable ICE Access Prevention
In-circuit Emulation, Debug Communication Channel Support
®
ARM
®
Thumb
®
Processor
AT91 ARM
Thumb-based
Microcontrollers
AT91SAM7S512
AT91SAM7S256
AT91SAM7S128
AT91SAM7S64
AT91SAM7S321
AT91SAM7S32
AT91SAM7S161
AT91SAM7S16
Summary
The complete document is available on
the Atmel website at
NOTE: This is a summary document.
6175FS–ATARM–03-Dec-07
www.atmel.com.

Related parts for AT91SAM7S256-AU-001

AT91SAM7S256-AU-001 Summary of contents

Page 1

... Kbytes (AT91SAM7S512) Organized in Two Contiguous Banks of 1024 Pages of 256 Bytes (Dual Plane) – 256 Kbytes (AT91SAM7S256) Organized in 1024 Pages of 256 Bytes (Single Plane) – 128 Kbytes (AT91SAM7S128) Organized in 512 Pages of 256 Bytes (Single Plane) – 64 Kbytes (AT91SAM7S64) Organized in 512 Pages of 128 Bytes (Single Plane) – ...

Page 2

... One Two-wire Interface (TWI) – Master Mode Support Only, All Two-wire Atmel EEPROMs and I (AT91SAM7S512/256/128/64/321/32) – Master, Multi-Master and Slave Mode Support, All Two-wire Atmel EEPROMs and I (AT91SAM7S161/16) • One 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os ™ ...

Page 3

... Their aggressive price point and high level of integration pushes their scope of use far into the cost-sensitive, high-volume consumer market. 1.1 Configuration Summary of the AT91SAM7S512, AT91SAM7S256, AT91SAM7S128, AT91SAM7S64, AT91SAM7S321, AT91SAM7S32, AT91SAM7S161 and AT91SAM7S16 The AT91SAM7S512, AT91SAM7S256, AT91SAM7S128, AT91SAM7S64, AT91SAM7S321, AT91SAM7S32, AT91SAM7S161 and AT91SAM7S16 differ in memory size, peripheral set and package ...

Page 4

Block Diagram Figure 2-1. AT91SAM7S512/256/128/64/321/161 Block Diagram TDI TDO JTAG TMS SCAN TCK JTAGSEL System Controller TST FIQ IRQ0-IRQ1 PCK0-PCK2 PLLRC PLL XIN OSC XOUT RCOSC VDDCORE BOD POR VDDCORE NRST DRXD DTXD RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 ...

Page 5

Figure 2-2. AT91SAM7S32/16 Block Diagram TDI TDO TMS TCK JTAGSEL System Controller TST FIQ IRQ0 PCK0-PCK2 PLLRC PLL XIN OSC XOUT VDDCORE BOD POR VDDCORE NRST DRXD DTXD RXD0 TXD0 SCK0 RTS0 CTS0 NPCS0 NPCS1 NPCS2 NPCS3 MISO MOSI SPCK ...

Page 6

Signal Description Table 3-1. Signal Description List Signal Name Function Voltage and ADC Regulator Power Supply VDDIN Input VDDOUT Voltage Regulator Output VDDFLASH Flash Power Supply VDDIO I/O Lines Power Supply VDDCORE Core Power Supply VDDPLL PLL GND Ground ...

Page 7

Table 3-1. Signal Description List (Continued) Signal Name Function DDM USB Device Port Data - DDP USB Device Port Data + SCK0 - SCK1 Serial Clock TXD0 - TXD1 Transmit Data RXD0 - RXD1 Receive Data RTS0 - RTS1 Request ...

Page 8

Table 3-1. Signal Description List (Continued) Signal Name Function TWD Two-wire Serial Data TWCK Two-wire Serial Clock AD0-AD3 Analog Inputs AD4-AD7 Analog Inputs ADTRG ADC Trigger ADVREF ADC Reference PGMEN0-PGMEN2 Programming Enabling PGMM0-PGMM3 Programming Mode PGMD0-PGMD15 Programming Data PGMRDY Programming ...

Page 9

Package and Pinout The AT91SAM7S512/256/128/64/321 are available in a 64-lead LQFP or 64-pad QFN package. The AT91SAM7S161 is available in a 64-Lead LQFP package. The AT91SAM7S32/16 are available in a 48-lead LQFP or 48-pad QFN package. 4.1 64-lead LQFP ...

Page 10

LQFP and 64-pad QFN Pinout Table 4-1. AT91SAM7S512/256/128/64/321/161 Pinout 1 ADVREF 17 2 GND 18 3 AD4 19 4 AD5 20 5 AD6 21 6 AD7 22 7 VDDIN 23 8 VDDOUT 24 9 PA17/PGMD5/AD0 25 10 PA18/PGMD6/AD1 ...

Page 11

LQFP and 48-pad QFN Package Outlines Figure 4-3 age. A detailed mechanical description is given in the section Mechanical Characteristics of the full datasheet. Figure 4-3. Figure 4-4. 4.4 48-lead LQFP and 48-pad QFN Pinout Table 4-2. AT91SAM7S32/16 ...

Page 12

Power Considerations 5.1 Power Supplies The AT91SAM7S Series has six types of power supply pins and integrates a voltage regulator, allowing the device to be supplied with only one voltage. The six power supply pin types are: • VDDIN ...

Page 13

Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip. For example, two capacitors can be used in parallel: 100 ...

Page 14

I/O Lines Considerations 6.1 JTAG Port Pins TMS, TDI and TCK are schmitt trigger inputs. TMS and TCK are 5-V tolerant, TDI is not. TMS, TDI and TCK do not integrate a pull-up resistor. TDO is an output, driven ...

Page 15

All the I/O lines PA0 to PA31 on AT91SAM7S161 (PA0 to PA20 on AT91SAM7S16) are not 5V-tolerant and all integrate a programmable pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the PIO ...

Page 16

Processor and Architecture 7.1 ARM7TDMI Processor • RISC processor based on ARMv4T Von Neumann architecture – Runs MHz, providing 0.9 MIPS/MHz • Two instruction sets – ARM – Thumb • Three-stage pipeline architecture – Instruction ...

Page 17

Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required – Key-protected program, erase and lock/unlock sequencer – Single command for erasing, programming and locking operations – Interrupt generation in case of forbidden operation 7.4 Peripheral DMA Controller ...

Page 18

... Protection Mode to secure contents of the Flash • 64 Kbytes of Fast SRAM – Single-cycle access at full speed 8.2 AT91SAM7S256 • 256 Kbytes of Flash Memory, single plane – 1024 pages of 256 bytes – Fast access time, 30 MHz single-cycle access in Worst Case conditions – Page programming time: 6 ms, including page auto-erase – ...

Page 19

AT91SAM7S64 • 64 Kbytes of Flash Memory, single plane – 512 pages of 128 bytes – Fast access time, 30 MHz single-cycle access in Worst Case conditions – Page programming time: 6 ms, including page auto-erase – Page programming ...

Page 20

Figure 8-1. AT91SAM7S512/256/128/64/321/32/161/16 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256 MBytes 0x0FFF FFFF 0x1000 0000 Undefined 14 x 256 MBytes (Abort) 3,584 MBytes 0xEFFF FFFF 0xF000 0000 Internal Peripherals 256M Bytes 0xFFFF FFFF AT91SAM7S Series Summary 20 ...

Page 21

... Internal Flash • The AT91SAM7S512 features two contiguous banks (dual plane) of 256 Kbytes of Flash. • The AT91SAM7S256 features one bank (single plane) of 256 Kbytes of Flash. • The AT91SAM7S128 features one bank (single plane) of 128 Kbytes of Flash. • The AT91SAM7S64 features one bank (single plane Kbytes of Flash. ...

Page 22

... The Flash of the AT91SAM7S512 is organized in two banks (dual plane) of 1024 pages of 256 bytes. The 524,288 bytes are organized in 32-bit words. • The Flash of the AT91SAM7S256 is organized in 1024 pages (single plane) of 256 bytes. The 262,144 bytes are organized in 32-bit words. • The Flash of the AT91SAM7S128 is organized in 512 pages (single plane) of 256 bytes. The 131,072 bytes are organized in 32-bit words. • ...

Page 23

... AT91SAM7S256 The Embedded Flash Controller manages 16 lock bits to protect 16 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7S256 contains 16 lock regions and each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16 Kbytes locked-region’s erase or program command occurs, the command is aborted and the LOCKE bit in the MC_FSR register rises and the interrupt line rises if the LOCKE bit has been written the MC_FMR register ...

Page 24

... Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region. Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash. Table summarizes the configuration of the eight devices. Flash Configuration Summary Device Number of Lock Bits AT91SAM7S512 32 AT91SAM7S256 16 AT91SAM7S128 8 AT91SAM7S64 16 AT91SAM7S321/32 8 AT91SAM7S161/16 ...

Page 25

Security Bit Feature The AT91SAM7S Series features a security bit, based on a specific NVM Bit. When the security is enabled, any access to the Flash, either through the ICE interface or through the Fast Flash Programming Interface, is ...

Page 26

The SAM-BA Boot Assistant is a default Boot Program that provides an easy way to program in situ the on-chip Flash memory. The SAM-BA Boot Assistant supports serial communication through the DBGU or through the USB Device Port. (The AT91SAM7S32/16 ...

Page 27

Figure 9-1. System Controller Block Diagram (AT91SAM7S512/256/128/64/321/161) irq0-irq1 periph_irq[2..14] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq MCK periph_nreset dbgu_rxd MCK debug periph_nreset SLCK periph_nreset SLCK debug proc_nreset cal gpnvm[0] en BOD POR NRST SLCK SLCK RCOSC XIN MAINCK OSC XOUT PLL ...

Page 28

Figure 9-2. System Controller Block Diagram (AT91SAM7S32/16) irq0 fiq periph_irq[2..14] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq MCK periph_nreset dbgu_rxd MCK debug periph_nreset SLCK periph_nreset SLCK debug idle proc_nreset cal gpnvm[0] en BOD POR NRST SLCK SLCK RCOSC XIN MAINCK OSC ...

Page 29

Reset Controller The Reset Controller is based on a power-on reset cell and one brownout detector. It gives the status of the last reset, indicating whether power-up reset, a software reset, a user reset, a watchdog ...

Page 30

Clock Generator The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following characteristics: • RC Oscillator ranges between 22 kHz and 42 kHz • Main Oscillator frequency ranges between 3 and 20 ...

Page 31

Figure 9-4. 9.4 Advanced Interrupt Controller • Controls the interrupt lines (nIRQ and nFIQ ARM Processor • Individually maskable and vectored interrupt sources – Source 0 is reserved for the Fast Interrupt Input (FIQ) – Source 1 is ...

Page 32

... Identification of the device revision, sizes of the embedded memories, set of – Chip ID is 0x270B0A40 for AT91SAM7S512 (VERSION 0) – Chip ID is 0x270B0940 for AT91SAM7S256 (VERSION 0) – Chip ID is 0x270C0941 for AT91SAM7S256 Rev B (VERSION 0) – Chip ID is 0x270A0740 for AT91SAM7S128 (VERSION 0) – Chip ID is 0x270C0741 for AT91SAM7S128 Rev B (VERSION 0) – ...

Page 33

Multiplexing of two peripheral functions per I/O line • For each I/O line (whether assigned to a peripheral or used as general-purpose I/O) – Input change interrupt – Half a clock period glitch filter – Multi-drive option enables driving ...

Page 34

Peripherals 10.1 User Interface The User Peripherals are mapped in the 256 MBytes of address space between 0xF000 0000 and 0xFFFF EFFF. Each peripheral is allocated 16 Kbytes of address space. A complete memory map is provided in 10.2 ...

Page 35

Table 10-2. Peripheral Note: 10.3 Peripheral Multiplexing on PIO Lines The AT91SAM7S Series features one PIO controller, PIOA, that ...

Page 36

PIO Controller A Multiplexing Table 10-3. Multiplexing on PIO Controller A (AT91SAM7S512/256/128/64/321/161) PIO Controller A I/O Line Peripheral A PA0 PWM0 PA1 PWM1 PA2 PWM2 PA3 TWD PA4 TWCK PA5 RXD0 PA6 TXD0 PA7 RTS0 PA8 CTS0 PA9 DRXD ...

Page 37

Table 10-4. Multiplexing on PIO Controller A (AT91SAM7S32/16) PIO Controller A I/O Line Peripheral A PA0 PWM0 PA1 PWM1 PA2 PWM2 PA3 TWD PA4 TWCK PA5 RXD0 PA6 TXD0 PA7 RTS0 PA8 CTS0 PA9 DRXD PA10 DTXD PA11 NPCS0 PA12 ...

Page 38

Serial Peripheral Interface • Supports communication with external serial devices – Four chip selects with external decoder allow communication with – Serial memories, such as DataFlash – Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN ...

Page 39

ISO7816 Protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit • IrDA modulation and demodulation – Communication 115.2 Kbps • Test Modes ...

Page 40

PWM Controller • Four channels, one 16-bit counter per channel • Common clock generator, providing thirteen different clocks – One Modulo n counter providing eleven clocks – Two independent linear dividers working on modulo n counter outputs • Independent ...

Page 41

Package Drawings The SAM7S series devices are available in LQFP and QFN package types. 11.1 LQFP Packages Figure 11-1. 48-and 64-lead LQFP Package Drawing 6175FS–ATARM–03-Dec-07 AT91SAM7S Series Summary 41 ...

Page 42

Table 11-1. Symbol θ 1 θ 2 θ aaa bbb ccc ddd AT91SAM7S Series Summary 42 48-lead LQFP Package Dimensions (in ...

Page 43

Table 11-2. Symbol θ θ θ aaa bbb ccc ddd 6175FS–ATARM–03-Dec-07 AT91SAM7S Series Summary 64-lead LQFP Package Dimensions (in mm) Millimeter Min ...

Page 44

QFN Packages Figure 11-2. 48-pad QFN Package AT91SAM7S Series Summary 44 6175FS–ATARM–03-Dec-07 ...

Page 45

Table 11-3. Symbol aaa bbb ccc 6175FS–ATARM–03-Dec-07 AT91SAM7S Series Summary 48-pad QFN Package Dimensions (in mm) Millimeter Min Nom Max – – 090 – – 0.050 – 0.65 ...

Page 46

Figure 11-3. 64-pad QFN Package Drawing ll dimensions are in mm ference : JEDEC Drawing MO-220 AT91SAM7S Series Summary 46 6175FS–ATARM–03-Dec-07 ...

Page 47

Table 11-4. Symbol aaa bbb ccc 6175FS–ATARM–03-Dec-07 AT91SAM7S Series Summary 64-pad QFN Package Dimensions (in mm) Millimeter Min Nom Max – – 090 – – 0.05 – 0.65 ...

Page 48

... AT91SAM7S Ordering Information Table 12-1. LQFP/OFN Ordering Information Ordering Code AT91SAM7S512-AU-001 AT91SAM7S512-MU AT91SAM7S256-AU-001 AT91SAM7S256-MU AT91SAM7S128-AU-001 AT91SAM7S128-MU AT91SAM7S64-AU-001 AT91SAM7S64-MU AT91SAM7S321-AU AT91SAM7S321-MU AT91SAM7S161-AU AT91SAM7S32-AU-001 AT91SAM7S32-MU AT91SAM7S16-AU-001 AT91SAM7S16-MU AT91SAM7S Series Summary 48 Package Package Type LQFP 64 Green QFN 64 LQFP 64 Green QFN 64 LQFP 64 Green QFN 64 LQFP 64 ...

Page 49

Revision History Doc. Rev Comments First issue - Unqualified on Intranet 6175AS Corresponds to 6175A full datasheet approval loop. Qualified on Intranet. 6175BS Section 8. “Memories” on page 18 6175CS Section 12. ”AT91SAM7S Ordering Information” “Features” , Table 1-1, “Configuration ...

Page 50

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

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