AT91M40800-33AI SL383 Atmel, AT91M40800-33AI SL383 Datasheet - Page 100
AT91M40800-33AI SL383
Manufacturer Part Number
AT91M40800-33AI SL383
Description
IC ARM MCU 16BIT 100TQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheets
1.AT91M40800-33AU.pdf
(18 pages)
2.AT91R40807-33AI.pdf
(153 pages)
3.AT91M40800-33AI.pdf
(21 pages)
Specifications of AT91M40800-33AI SL383
Core Processor
ARM7
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, UART/USART
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Other names
AT91M4080033AISL3
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Baud Rate Generator
Figure 37. Baud Rate Generator
100
MCK/8
MCK
SCK
AT91X40 Series
USCLKS [0]
0
1
USCLKS [1]
0
1
The Baud Rate Generator provides the bit period clock (the Baud Rate clock) to both the
Receiver and the Transmitter.
The Baud Rate Generator can select between external and internal clock sources. The
external clock source is SCK. The internal clock sources can be either the master clock
(MCK) or the master clock divided by 8 (MCK/8).
Note:
When the USART is programmed to operate in Asynchronous Mode (SYNC = 0 in the
Mode Register US_MR), the selected clock is divided by 16 times the value (CD) written
in US_BRGR (Baud Rate Generator Register). If US_BRGR is set to 0, the Baud Rate
Clock is disabled.
When the USART is programmed to operate in Synchronous Mode (SYNC = 1) and the
selected clock is internal (USCLKS[1] = 0 in the Mode Register US_MR), the Baud Rate
Clock is the internal selected clock divided by the value written in US_BRGR. If
US_BRGR is set to 0, the Baud Rate Clock is disabled.
In Synchronous Mode with external clock selected (USCLKS[1] = 1), the clock is pro-
vided directly by the signal on the SCK pin. No division is active. The value written in
US_BRGR has no effect.
CLK
Baud Rate
Baud Rate
In all cases, if an external clock is used, the duration of each of its levels must be longer
than the system clock (MCK) period. The external clock frequency must be at least 2.5
times lower than the system clock.
16-bit Counter
CD
=
=
USCLKS [1]
SYNC
Selected Clock
Selected Clock
OUT
0
16 x CD
CD
CD
>1
1
0
0
1
Divide
by 16
SYNC
0
1
1354D–ATARM–08/02
Baud Rate
Clock
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