DSPIC30F4013T-20I/ML Microchip Technology, DSPIC30F4013T-20I/ML Datasheet - Page 139

• Manufacturer Part Number: DSPIC30F4013T-20I/ML
• Description: IC DSPIC MCU/DSP 48K 44QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013T-20I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: DSPIC30F4013T20IM

20.3
The oscillators are controlled with two SFRs,
OSCCON and OSCTUN and one configuration
register, FOSC.
REGISTER 20-1:
 2004 Microchip Technology Inc.
Upper Byte:
bit 15
bit 15
bit 14-12 COSC<2:0>: Current Oscillator Group Selection (Read Only)
bit 11
bit 10-8
bit 7-6
bit 5
bit 4
U-0
—
Oscillator Control Registers
Unimplemented: Read as ‘0’
111 = PLL Oscillator; PLL source selected by FPR<4:0> bits
011 = External Oscillator; OSC1/OSC2 pins; External Oscillator configuration selected by FPR<4:0> bits
010 = LPRC internal low power RC
001 = FRC internal fast RC
000 = LP crystal oscillator; SOSCI/SOSCO pins
Set to FOS<2:0> values on POR or BOR.
Loaded with NOSC<2:0> at the completion of a successful clock switch.
Set to FRC value when FSCM detects a failure and switches clock to FRC.
Unimplemented: Read as ‘0’
NOSC<2:0>: New Oscillator Group Selection
111 = PLL Oscillator; PLL source selected by FPR<4:0> bits
011 = External Oscillator; OSC1/OSC2 pins; External Oscillator configuration selected by FPR<4:0> bits
010 = LPRC internal low power RC
001 = FRC internal fast RC
000 = LP crystal oscillator; SOSCI/SOSCO pins
Set to FOS<2:0> values on POR or BOR.
POST<1:0>: Oscillator Postscaler Selection bits
11 = Oscillator postscaler divides clock by 64
10 = Oscillator postscaler divides clock by 16
01 = Oscillator postscaler divides clock by 4
00 = Oscillator postscaler does not alter clock
LOCK: PLL Lock Status bit (Read Only)
1 = Indicates that PLL is in lock
0 = Indicates that PLL is out of lock (or disabled)
Reset on POR or BOR.
Reset when a valid clock switching sequence is initiated.
Set when PLL lock is achieved after a PLL start.
Reset when lock is lost.
Read zero when PLL is not selected as a system clock.
Unimplemented: Read as ‘0’
R-y
Lower Byte:
bit 7
R/W-0
OSCCON: OSCILLATOR CONTROL REGISTER
POST<1:0>
COSC<2:0>
R-y
R/W-0
R-y
Advance Information
LOCK
R-0
U-0
—
U-0
—
Note:
dsPIC30F3014/4013
R/W-y
R/W-0
CF
The description of the OSCCON and
OSCTUN SFRs, as well as the FOSC
configuration register provided in this
section
dsPIC30F3014
devices in the dsPIC30F product family.
NOSC<2:0>
R/W-y
are
U-0
—
R/W-y
applicable
LPOSCEN
and
bit 8
R/W-0
DS70138C-page 137
dsPIC30F4013
only
OSWEN
R/W-0
to
bit 0
the