ATMEGA169-16AU Atmel, ATMEGA169-16AU Datasheet - Page 174
ATMEGA169-16AU
Manufacturer Part Number
ATMEGA169-16AU
Description
IC AVR MCU 16K 16MHZ 5V 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA169-16AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
ATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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USART Baud Rate Registers –
UBRRL and UBRRH
174
ATmega169/V
• Bit 2:1 – UCSZ1:0: Character Size
The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits
(Character SiZe) in a frame the Receiver and Transmitter use.
Table 77. UCSZ Bits Settings
• Bit 0 – UCPOL: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous
mode is used. The UCPOL bit sets the relationship between data output change and
data input sample, and the synchronous clock (XCK).
Table 78. UCPOL Bit Settings
• Bit 15:12 – Reserved Bits
These bits are reserved for future use. For compatibility with future devices, these bit
must be written to zero when UBRRH is written.
• Bit 11:0 – UBRR11:0: USART Baud Rate Register
This is a 12-bit register which contains the USART baud rate. The UBRRH contains the
four most significant bits, and the UBRRL contains the eight least significant bits of the
USART baud rate. Ongoing transmissions by the Transmitter and Receiver will be cor-
rupted if the baud rate is changed. Writing UBRRL will trigger an immediate update of
the baud rate prescaler.
Bit
Read/Write
Initial Value
UCPOL
0
1
UCSZ2
0
0
0
0
1
1
1
1
Transmitted Data Changed (Output of
TxD Pin)
Rising XCK Edge
Falling XCK Edge
R/W
15
R
–
7
0
0
R/W
14
R
UCSZ1
–
6
0
0
0
0
1
1
0
0
1
1
R/W
13
R
–
5
0
0
R/W
12
R
–
4
0
0
UBRR[7:0]
UCSZ0
0
1
0
1
0
1
0
1
R/W
R/W
11
3
0
0
Received Data Sampled (Input on
RxD Pin)
Falling XCK Edge
Rising XCK Edge
R/W
R/W
Character Size
5-bit
6-bit
7-bit
8-bit
Reserved
Reserved
Reserved
9-bit
10
2
0
0
UBRR[11:8]
R/W
R/W
9
1
0
0
R/W
R/W
8
0
0
0
2514P–AVR–07/06
UBRRH
UBRRL
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