ATMEGA88-20MU Atmel, ATMEGA88-20MU Datasheet - Page 199

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ATMEGA88-20MU

Manufacturer Part Number
ATMEGA88-20MU
Description
IC AVR MCU 8K 20MHZ 5V 32-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA88-20MU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Package
32MLF EP
Device Core
AVR
Family Name
ATmega
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
23
Interface Type
SPI/TWI/USART
On-chip Adc
8-chx10-bit
Number Of Timers
3
Processor Series
ATMEGA8x
Core
AVR8
Data Ram Size
1 KB
Maximum Clock Frequency
20 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRTS2080A, ATASTK512-EK1-IND
Minimum Operating Temperature
- 40 C
A/d Inputs
8-Channel, 10-Bit
Cpu Speed
20 MIPS
Eeprom Memory
512 Bytes
Input Output
23
Interface
SPI/TWI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
32-pin MLF
Programmable Memory
8K Bytes
Timers
2-8-bit, 1-16-bit
Voltage, Range
4.5-5.5 V
Controller Family/series
AVR MEGA
No. Of I/o's
23
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
No. Of Timers
3
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
20.4
2545S–AVR–07/10
SPI Data Modes and Timing
Table 20-1.
Note:
There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which
are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are
shown in
signal, ensuring sufficient time for data signals to stabilize. The UCPOLn and UCPHAn function-
ality is summarized in
all ongoing communication for both the Receiver and Transmitter.
Table 20-2.
Operating Mode
Synchronous Master
mode
UCPOLn
BAUD
f
UBRRn
OSC
0
0
1
1
1. The baud rate is defined to be the transfer rate in bit per second (bps)
Figure
Equations for Calculating Baud Rate Register Setting
UCPOLn and UCPHAn Functionality-
20-1. Data bits are shifted out and latched in on opposite edges of the XCKn
UCPHAn
Table
Baud rate (in bits per second, bps)
System Oscillator clock frequency
Contents of the UBRRnH and UBRRnL Registers, (0-4095)
0
1
0
1
Equation for Calculating Baud
20-2. Note that changing the setting of any of these bits will corrupt
BAUD
SPI Mode
=
0
1
2
3
Rate
-------------------------------------- -
2 UBRRn
(
(1)
f
OSC
Leading Edge
Sample (Rising)
Setup (Rising)
Sample (Falling)
Setup (Falling)
+
1
)
ATmega48/88/168
Equation for Calculating UBRRn
UBRRn
Trailing Edge
Setup (Falling)
Sample (Falling)
Setup (Rising)
Sample (Rising)
Value
=
------------------- - 1
2BAUD
f
OSC
199

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