ATMEGA88V-10AU Atmel, ATMEGA88V-10AU Datasheet - Page 171

IC AVR MCU 8K 10MHZ 1.8V 32TQFP

ATMEGA88V-10AU

Manufacturer Part Number
ATMEGA88V-10AU
Description
IC AVR MCU 8K 10MHZ 1.8V 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA88V-10AU

Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Processor Series
ATMEGA8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
2-Wire, SPI, USART, Serial
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
3 bit
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
32TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
10 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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19.3
2545S–AVR–07/10
Clock Generation
Figure 19-1. USART Block Diagram
Note:
The Clock Generation logic generates the base clock for the Transmitter and Receiver. The
USART supports four modes of clock operation: Normal asynchronous, Double Speed asyn-
chronous, Master synchronous and Slave synchronous mode. The UMSELn bit in USART
Control and Status Register C (UCSRnC) selects between asynchronous and synchronous
operation. Double Speed (asynchronous mode only) is controlled by the U2Xn found in the
UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register
for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or
external (Slave mode). The XCKn pin is only active when using synchronous mode.
Figure 19-2
1. Refer to
shows a block diagram of the clock generation logic.
Figure 1-1 on page 2
UCSRnA
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER
BAUD RATE GENERATOR
UDRn (Receive)
UDRn(Transmit)
UBRRn [H:L]
(1)
and
Table 13-9 on page 83
UCSRnB
GENERATOR
SYNC LOGIC
RECOVERY
RECOVERY
CHECKER
PARITY
PARITY
CLOCK
DATA
OSC
ATmega48/88/168
for USART0 pin placement.
Clock Generator
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
Transmitter
PIN
PIN
PIN
RX
TX
Receiver
UCSRnC
XCKn
TxDn
RxDn
171

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