ATMEGA88V-10AU Atmel, ATMEGA88V-10AU Datasheet - Page 255

IC AVR MCU 8K 10MHZ 1.8V 32TQFP

ATMEGA88V-10AU

Manufacturer Part Number
ATMEGA88V-10AU
Description
IC AVR MCU 8K 10MHZ 1.8V 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA88V-10AU

Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Processor Series
ATMEGA8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
2-Wire, SPI, USART, Serial
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
3 bit
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
32TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
10 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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23.8.2
2545S–AVR–07/10
ADCSRA – ADC Control and Status Register A
The value of these bits selects which analog inputs are connected to the ADC. See
for details. If these bits are changed during a conversion, the change will not go in effect until this
conversion is complete (ADIF in ADCSRA is set).
Table 23-3.
• Bit 7 – ADEN: ADC Enable
Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the
ADC off while a conversion is in progress, will terminate this conversion.
• Bit 6 – ADSC: ADC Start Conversion
In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode,
write this bit to one to start the first conversion. The first conversion after ADSC has been written
after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled,
will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initializa-
tion of the ADC.
ADSC will read as one as long as a conversion is in progress. When the conversion is complete,
it returns to zero. Writing zero to this bit has no effect.
Bit
(0x7A)
Read/Write
Initial Value
MUX3..0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Input Channel Selections
ADEN
R/W
7
0
ADSC
R/W
6
0
ADATE
Single Ended Input
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
1.1V (V
0V (GND)
R/W
5
0
BG
)
ADIF
R/W
4
0
ADIE
R/W
3
0
ADPS2
R/W
ATmega48/88/168
2
0
ADPS1
R/W
1
0
ADPS0
R/W
0
0
Table 23-3
ADCSRA
255

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