AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet - Page 75
AT89C51SND2C-7FTUL
Manufacturer Part Number
AT89C51SND2C-7FTUL
Description
IC 8051 MCU FLASH 64K MP3 100BGA
Manufacturer
Atmel
Series
89Cr
Datasheet
1.AT89C51SND2C-7FTUL.pdf
(242 pages)
Specifications of AT89C51SND2C-7FTUL
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
Peripherals
Audio, I²S, MP3, PCM, POR, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 2x10b; D/A 2x20b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Data Bus Width
8 bit
Data Ram Size
2.25 KB
Interface Type
ATAPI, I2S, IDE, SPI, UART, USB
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
32
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
AT89C51SND2C7FTUL
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14.2
14.3
4341H–MP3–10/07
Clock Generator
Data Converter
The audio interface clock is generated by division of the PLL clock. The division factor is given
by AUCD4:0 bits in CLKAUD register. Figure 14-2 shows the audio interface clock generator
and its calculation formula. The audio interface clock frequency depends on the incoming MP3
frames and the audio DAC used.
Figure 14-2. Audio Clock Generator and Symbol
As soon as audio interface is enabled by setting AUDEN bit in AUDCON1 register, the master
clock generated by the PLL is output on the SCLK pin which is the DAC system clock. This clock
is output at 256 or 384 times the sampling frequency depending on the DAC capabilities. HLR bit
in AUDCON0 register must be set according to this rate for properly generating the audio bit
clock on the DCLK pin and the word selection clock on the DSEL pin. These clocks are not gen-
erated when no data is available at the data converter input.
For DAC compatibility, the bit clock frequency is programmable for outputting 16 bits or 32 bits
per channel using the DSIZ bit in AUDCON0 register (see Section "Data Converter", page 75),
and the word selection signal is programmable for outputting left channel on low or high level
according to POL bit in AUDCON0 register as shown in Figure 14-3.
Figure 14-3. DSEL Output Polarity
The data converter block converts the audio stream input from the 16-bit parallel format to a
serial format. For accepting all PCM formats and I
are used to shift the data output point. As shown in Figure 14-4, these bits allow MSB justifica-
tion by setting JUST4:0 = 00000, LSB justification by setting JUST4:0 = 10000, I
by setting JUST4:0 = 00001, and more than 16-bit LSB justification by filling the low significant
bits with logic 0.
Table 14-1.
Dac Format
16-bit I
> 16-bit I
16-bit PCM
18-bit PCM LSB justified
20-bit PCM LSB justified
20-bit PCM MSB justified
2
S
2
S
CLOCK
PLL
DAC Format Programing Examples
POL = 0
POL = 1
AUCD4:0
AUDCLK
Left Channel
Left Channel
AUDclk
Audio Interface Clock
=
2
---------------------------
AUCD
S format, JUST4:0 bits in AUDCON0 register
PLLclk
AT8xC51SND2C/MP3B
+
Right Channel
Right Channel
POL
1
0
0
1
1
1
1
DSIZ
0
1
0
1
1
1
Audio Clock Symbol
CLOCK
AUD
2
S justification
JUST4:0
00001
00001
00000
00000
01110
01100
75
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